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公开(公告)号：US12009020B2
公开(公告)日：2024-06-11
申请号：US17707027
申请日：2022-03-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Daeshik Kim
CPC classification number: G11C11/1675 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1697 , H10B61/20 , H10N50/10 , H10N50/80
Abstract: A memory device includes; a memory cell array including a first memory cell region and a second memory cell region, a voltage generator configured to generate a code corresponding to a write voltage, and a write driver configured to store data in the first memory cell region in response to the code. The second memory cell region stores a value defining the write voltage, and the write voltage is determined in relation to a reference resistance distinguishing a parallel state and an anti-parallel state for the memory cells, and further in relation to an initial write voltage applied to a magnetic tunnel junction element of at least one of the memory cells.
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公开(公告)号：US09806027B2
公开(公告)日：2017-10-31
申请号：US14460692
申请日：2014-08-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Daeshik Kim
IPC: H01L23/535 , H01L43/08 , H01L27/22 , H01L43/12
CPC classification number: H01L23/535 , H01L27/228 , H01L43/08 , H01L43/12 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device includes an interlayer dielectric on a semiconductor substrate, a contact plug penetrating the interlayer dielectric, a pillar pattern disposed on the interlayer dielectric and having a central axis laterally offset from a central axis of the contact plug, a pad extending on the contact plug and along a sidewall of the pillar pattern, the pad being electrically connected to the contact plug, and a data storage portion on the pillar pattern and electrically connected to the pad.
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公开(公告)号：US12094509B2
公开(公告)日：2024-09-17
申请号：US17709784
申请日：2022-03-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Daeshik Kim
CPC classification number: G11C11/1673 , G11C11/161 , G11C11/1653 , G11C11/1675 , G11C11/1677 , G11C17/16
Abstract: Disclosed is a memory device including a magnetic storage element. The memory device includes a memory cell array, a voltage generator, and a write driver. The memory cell array includes a first region and a second region. The memory device is configured to store a value of a first read current determined based on a value of a reference resistance for distinguishing a parallel state and an anti-parallel state of a programmed memory cell. The sensing circuit is configured to generate the first read current based on the value of the first read current and to perform a read operation on the first region based on the first read current.
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公开(公告)号：US12260890B2
公开(公告)日：2025-03-25
申请号：US18545626
申请日：2023-12-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Daeshik Kim
IPC: G11C11/16
Abstract: Disclosed is a memory device including a magnetic memory element. The memory device includes a memory cell array including a first region and a second region, the second region configured to store a value of a write voltage, the write voltage based on a value of a reference resistor for determining whether a programmed memory cell is in a parallel state or anti-parallel state, a voltage generator configured to generate a code value based on the value of the write voltage, and a write driver configured to drive a write current based on the code value, the write current being a current for storing data in the first region.
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Patent Agency Ranking
公开(公告)号：US20230073175A1
公开(公告)日：2023-03-09
申请号：US17929186
申请日：2022-09-01
Inventor： Daeshik Kim , Wooyeong Cho , Sanghyeok Son
Abstract: Systems and methods for processing a plurality of images include obtaining input data including the plurality of images; providing the input data to a first machine learning model; providing an output of the first machine learning model to a second machine learning model and a third machine learning model; generating a first feature map corresponding to a plurality of kernels based on an output of the second machine learning model; generating a second feature map corresponding to a plurality of weights based on an output of the third machine learning model; generating a predicted kernel based on a weighted sum of the plurality of kernels; and generating output data based on the input data and the predicted kernel.
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公开(公告)号：US10388629B2
公开(公告)日：2019-08-20
申请号：US15718535
申请日：2017-09-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Daeshik Kim , Gwanhyeob Koh
IPC: H01L25/065 , H01L43/08 , H01L23/522 , H01L27/22 , H01L25/00 , H01L23/00
Abstract: A semiconductor device comprises a first semiconductor chip comprising a first substrate. A first magnetic tunnel junction is on the first substrate. A second semiconductor chip comprises a second substrate. A second magnetic tunnel junction is on the second substrate. The second semiconductor chip is positioned on the first semiconductor chip to form a chip stack. A first critical current density required for magnetization reversal of the first magnetic tunnel junction is different than a second critical current density required for magnetization reversal of the second magnetic tunnel junction.
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公开(公告)号：US10210931B2
公开(公告)日：2019-02-19
申请号：US15612040
申请日：2017-06-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Daeshik Kim
IPC: G11C13/00
Abstract: A nonvolatile memory device includes: first memory cells connected to a first source line and a first bit line; second memory cells connected to a second source line and a second bit line; and a sense amplifier circuit connected to the first and second source lines and the first and second bit lines. The sense amplifier circuit includes: a first sense amplifier configured to apply a first read voltage to the first bit line and output a first amount of current of a selected first memory cell; a second sense amplifier configured to apply a second read voltage to the second bit line and output a second amount of current of a selected second memory cell; and a comparator configured to compare the first amount of current with the second amount of current to identify data of the selected first memory cell.
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公开(公告)号：US11894038B2
公开(公告)日：2024-02-06
申请号：US17399264
申请日：2021-08-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Daeshik Kim
CPC classification number: G11C11/1675 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1697
Abstract: Disclosed is a memory device including a magnetic memory element. The memory device includes a memory cell array including a first region and a second region, the second region configured to store a value of a write voltage, the write voltage based on a value of a reference resistor for determining whether a programmed memory cell is in a parallel state or anti-parallel state, a voltage generator configured to generate a code value based on the value of the write voltage, and a write driver configured to drive a write current based on the code value, the write current being a current for storing data in the first region.
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公开(公告)号：US20180277517A1
公开(公告)日：2018-09-27
申请号：US15718535
申请日：2017-09-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Daeshik Kim , Gwanhyeob Koh
IPC: H01L25/065 , H01L43/08 , H01L27/22 , H01L23/522
CPC classification number: H01L25/0657 , H01L23/5226 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/80 , H01L25/50 , H01L27/228 , H01L43/08 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05684 , H01L2224/05686 , H01L2224/08145 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2224/2919 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/80091 , H01L2224/80097 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2224/94 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06565 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/00014 , H01L2224/80 , H01L2224/81 , H01L2924/014 , H01L2924/04642 , H01L2924/0504 , H01L21/76898
Abstract: A semiconductor device comprises a first semiconductor chip comprising a first substrate. A first magnetic tunnel junction is on the first substrate. A second semiconductor chip comprises a second substrate. A second magnetic tunnel junction is on the second substrate. The second semiconductor chip is positioned on the first semiconductor chip to form a chip stack. A first critical current density required for magnetization reversal of the first magnetic tunnel junction is different than a second critical current density required for magnetization reversal of the second magnetic tunnel junction.
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