公开(公告)号：US12062624B2

公开(公告)日：2024-08-13

申请号：US17391659

申请日：2021-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulsoon Chang ,  Sangki Kim ,  Ilgeun Jung ,  Junghoon Han

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L21/76877

Abstract: A semiconductor device may include a semiconductor substrate, a crack-blocking layer and a crack-blocking portion. The semiconductor substrate may include a plurality of chip regions and a scribe lane region configured to surround each of the plurality of the chip regions. A trench may be defined by one or more inner surfaces of the semiconductor device to be formed in the scribe lane region. The crack-blocking layer may be on an inner surface of the trench. The crack-blocking layer may be configured to block a spreading of a crack, which is generated in the scribe lane region during a cutting of the semiconductor substrate along the scribe lane region, from spreading into any of the chip regions. The crack-blocking portion may at least partially fill the trench and may be configured to block the spreading of the crack from the scribe lane region into any of the chip regions.

公开(公告)号：US11817405B2

公开(公告)日：2023-11-14

申请号：US17496488

申请日：2021-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sumin Ahn ,  Byungjun Kang ,  Jiyoung Kim ,  Hae Seok Park ,  Chulsoon Chang

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/02 ,  H01L21/481 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0221 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/02311 ,  H01L2224/05548 ,  H01L2224/13024 ,  H01L2224/16227

Abstract: Disclosed are semiconductor devices and their fabricating methods. The semiconductor device comprises a dielectric layer, a trench formed in the dielectric layer, a metal pattern that conformally covers a top surface of the dielectric layer, an inner side surface of the trench, and a bottom surface of the trench, a first protection layer that conformally covers the metal pattern, and a second protection layer that covers the first protection layer. A cavity is formed in the trench. The cavity is surrounded by the first protection layer. The first protection layer has an opening that penetrates the first protection layer and extends from a top surface of the first protection layer. The opening is connected to the cavity. A portion of the second protection layer extends into the opening and closes the cavity.

公开(公告)号：US20230215818A1

公开(公告)日：2023-07-06

申请号：US18067839

申请日：2022-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulsoon Chang ,  Seilyn Kwak ,  Haeseok Park

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L24/48 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3128 ,  H01L23/585 ,  H01L2224/48227 ,  H01L2224/32225 ,  H01L2224/73265

Abstract: An integrated circuit device includes a semiconductor substrate having a first device region, a second device region, and a scribe line region therein. The scribe line region, which extends between the first and second device regions, includes a first edge region adjacent the first device region, a second edge region adjacent the second device region and a cutting region extending between the first and second device regions. A lower interlayer insulating layer is provided on the first and second device regions and on the scribe line region. A first multi-level guard ring is provided, which at least partially surrounds the first device region, when viewed from a plan perspective. An insulating structure is provided, which has a recess therein. The recess extends adjacent the first multi-level guard rings and exposes an upper surface of the lower interlayer insulating layer.