公开(公告)号：US12062624B2

公开(公告)日：2024-08-13

申请号：US17391659

申请日：2021-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulsoon Chang ,  Sangki Kim ,  Ilgeun Jung ,  Junghoon Han

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L21/76877

Abstract: A semiconductor device may include a semiconductor substrate, a crack-blocking layer and a crack-blocking portion. The semiconductor substrate may include a plurality of chip regions and a scribe lane region configured to surround each of the plurality of the chip regions. A trench may be defined by one or more inner surfaces of the semiconductor device to be formed in the scribe lane region. The crack-blocking layer may be on an inner surface of the trench. The crack-blocking layer may be configured to block a spreading of a crack, which is generated in the scribe lane region during a cutting of the semiconductor substrate along the scribe lane region, from spreading into any of the chip regions. The crack-blocking portion may at least partially fill the trench and may be configured to block the spreading of the crack from the scribe lane region into any of the chip regions.

公开(公告)号：US11705379B2

公开(公告)日：2023-07-18

申请号：US17087879

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Won Kim ,  Haeseok Park ,  Ilgeun Jung ,  Jinkuk Bae ,  Inyoung Lee ,  Sungdong Cho

IPC: H01L23/31 ,  H01L25/065 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/3171 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L22/12 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/13016 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/14515 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/1436

Abstract: A semiconductor package may include a base, a first chip on the base, and first connection patterns that connect and couple the base and the first chip. The first chip may include a substrate, pad patterns on the substrate, a passivation layer on the substrate and having openings, and pillars on the substrate, the pad patterns include a first signal pad and a second signal pad, the first connection patterns are in contact with the pillars, the pillars include a first signal pillar in contact with the first signal pad and a second signal pillar in contact with the second signal pad, the openings in the passivation layer include a first opening having a sidewall facing a side surface of the first signal pillar and surrounding the side surface of the first signal pillar, and a second opening having a sidewall facing a side surface of the second signal pillar and surrounding the side surface of the second signal pillar, and a maximum width of the second opening is greater than a maximum width of the first opening.