公开(公告)号：US20230361018A1

公开(公告)日：2023-11-09

申请号：US18166181

申请日：2023-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin YIM ,  Sungbum KIM ,  Jiyong PARK ,  Jinwoo PARK ,  Jongbo SHIM

IPC: H01L23/498 ,  H10B80/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H10B80/00 ,  H01L24/16

Abstract: Provided is a semiconductor package including a support wiring structure, a semiconductor chip on the support wiring structure, a cover wiring structure on the semiconductor chip, and a filling member filling between the support wiring structure and the cover wiring structure, wherein the cover wiring structure includes a cavity which extends from a lower surface of the cover wiring structure into the cover wiring structure and in which an upper portion of the semiconductor chip is positioned, and a first slot and a second slot respectively having a first width and a second width in a first horizontal direction, the first slot and the second slot communicating with the cavity, and respectively extending to a first side surface and a second side surface of the cover wiring structure, which are opposite to each other in a second horizontal direction which is orthogonal to the first horizontal direction of the cover wiring structure.

公开(公告)号：US20220302035A1

公开(公告)日：2022-09-22

申请号：US17835768

申请日：2022-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin YIM ,  Jungwoo KIM ,  Jihwang KIM ,  Jongbo SHIM ,  Kyoungsei CHOI

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/14

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.

公开(公告)号：US20240234279A9

公开(公告)日：2024-07-11

申请号：US18490995

申请日：2023-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin YIM ,  Jiyong PARK

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15174 ,  H01L2924/15184

Abstract: A semiconductor package includes a first redistribution structure including a first redistribution layer and a first redistribution bonding pad, the first redistribution bonding pad electrically connected to the first redistribution layer, a first semiconductor chip on the first redistribution structure, and a second redistribution structure on the first semiconductor chip, the second redistribution structure including a second redistribution layer and a second redistribution bonding pad, the second redistribution layer electrically connected to the second redistribution layer. The semiconductor package includes a bonding wire electrically connecting the second redistribution bonding pad and the first redistribution bonding pad to each other, and a molding layer covering at least a portion the first semiconductor chip, the second redistribution structure, and the bonding wire on the first redistribution structure.

公开(公告)号：US20230361051A1

公开(公告)日：2023-11-09

申请号：US18113910

申请日：2023-02-24

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Choongbin YIM ,  Hyonchol KIM ,  Sungbum KIM ,  Gitae PARK ,  Jiyong PARK ,  Jinwoo PARK ,  Jongbo SHIM

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/16 ,  H01L21/4853 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/81815

Abstract: A semiconductor package includes: a package substrate including a redistribution layer, a lower protective layer, and a plurality of support protrusions, wherein the redistribution layer has first and second pads disposed on the package substrate, wherein the lower protective layer has first openings and a trench, wherein the trench exposes the second pads, and wherein the plurality of support protrusions are disposed in the trench; a semiconductor chip disposed on the package substrate and including connection pads electrically connected to the redistribution layer; an encapsulant disposed on at least a portion of the semiconductor chip; first connection bumps electrically connected to the first pads, respectively; a passive device disposed in the trench of the lower protective layer and electrically connected to the second pads; and a sealant covering at least a portion of the passive device and extending into the trench.

公开(公告)号：US20240379635A1

公开(公告)日：2024-11-14

申请号：US18601335

申请日：2024-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin YIM ,  Jongkook KIM ,  Chengtar WU

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L23/28 ,  H01L23/498 ,  H01L25/00

Abstract: Provided a three-dimensional (3D) integrated circuit structure including a redistribution structure, a first semiconductor die on the redistribution structure, a substrate on the redistribution structure and adjacent to the first semiconductor die, a molding material on the redistribution structure and between the first semiconductor die and the substrate, an interconnection structure on the substrate and the first semiconductor die, the interconnection structure including a plurality of first bonding pads and a plurality of second bonding pads, and each second bonding pad of the second bonding pads being directly bonded to each first bonding pad of the first bonding pads, and a second semiconductor die on the interconnection structure.

公开(公告)号：US20220189835A1

公开(公告)日：2022-06-16

申请号：US17376883

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin YIM ,  Dongwook KIM ,  Hyunki KIM ,  Jongbo SHIM ,  Jihwang KIM ,  Sungkyu PARK ,  Yongkwan LEE ,  Byoungwook JANG

IPC: H01L23/12 ,  H01L23/538

Abstract: A semiconductor package including a first package substrate, a first semiconductor chip on the first package substrate, a first conductive connector on the first package substrate and laterally spaced apart from the first semiconductor chip, an interposer substrate on the first semiconductor chip and electrically connected to the first package substrate through the first conductive connector, the interposer substrate including a first portion overlapping the first semiconductor chip and a plurality of upper conductive pads in the first portion, a plurality of spacers on a lower surface of the first portion of the interposer substrate and positioned so as not to overlap the plurality of upper conductive pads in a plan view, and an insulating filler between the interposer substrate and the first package substrate may be provided.

公开(公告)号：US20130178016A1

公开(公告)日：2013-07-11

申请号：US13736551

申请日：2013-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin YIM ,  Eunchul AHN ,  Taesung PARK ,  Hak-kyoon BYUN ,  Yongkwan LEE

IPC: H01L25/00

CPC classification number: H01L25/105 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2224/83

Abstract: Methods of fabricating a package-on-package device and package-on-package devices fabricated by the same may be provided. According to inventive concepts, a back-grinding of a semiconductor chip to a target thickness may be performed after the semiconductor chip is molded by a molding layer. Accordingly, the semiconductor chip is relatively thick while forming a molding layer, and thus less susceptible to a warpage phenomenon, which for instance may occur during the forming a molding layer. Thus, relatively thin package-on-package device, which is less susceptible to the warpage phenomenon, may be achieved.

Abstract translation: 可以提供制造封装封装器件和由其制造的封装封装器件的方法。 根据本发明的概念，可以在通过模制层模制半导体芯片之后进行半导体芯片到目标厚度的背面磨削。 因此，半导体芯片在形成模制层的同时相对较厚，因此较不容易发生翘曲现象，例如可能在形成模制层期间发生。 因此，可以实现较不易受翘曲现象影响的较薄的封装封装器件。

公开(公告)号：US20250046721A1

公开(公告)日：2025-02-06

申请号：US18592004

申请日：2024-02-29

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Choongbin YIM ,  Jongkook KIM ,  Chengtar WU

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package includes a support substrate having a through hole and including an insulating layer, one or more wiring layers including a first wiring layer, and a first electronic device on the first wiring layer, a semiconductor chip positioned in the through hole to be at least partially surrounded by the support substrate and including a connection pad on a first surface of the semiconductor chip, an encapsulant filling at least a portion of the through hole and encapsulating at least a portion of the semiconductor chip, a first redistribution layer structure on the first surface of the semiconductor chip and including a first redistribution layer, and a second redistribution layer structure over a second surface of the semiconductor chip that is opposite to the first surface of the semiconductor chip, the second redistribution layer structure including a second redistribution layer.

公开(公告)号：US20240258222A1

公开(公告)日：2024-08-01

申请号：US18493234

申请日：2023-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chengtar WU ,  Jongkook KIM ,  Choongbin YIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/15311

Abstract: A 3D integrated circuit structure, comprising: a redistribution layer structure; a first semiconductor chip die on the redistribution layer structure; a plurality of sacrificial pads on the redistribution layer structure; a plurality of conductive posts disposed adjacent the first semiconductor chip die, wherein the plurality of conductive posts is on the plurality of sacrificial pads, respectively; a molding material that is on the first semiconductor chip die, the plurality of sacrificial pads, the plurality of conductive posts, and the redistribution layer structure; an interconnection structure on the molding material; and a second semiconductor chip die on the interconnection structure, wherein the second semiconductor chip die overlaps the first semiconductor chip die and the plurality of conductive posts in a vertical direction.

公开(公告)号：US20240258221A1

公开(公告)日：2024-08-01

申请号：US18493166

申请日：2023-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin YIM ,  Jongkook KIM ,  Chengtar WU

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/08 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81

Abstract: A 3D integrated circuit structure includes a redistribution layer structure; a first semiconductor chip die on the redistribution layer structure; a plurality of core balls on the redistribution layer structure and adjacent the first semiconductor chip die; a molding material encapsulating the first semiconductor chip die and the plurality of core balls on the redistribution layer structure; an interconnection structure on the molding material; and a second semiconductor chip die on the interconnection structure. A footprint of the first semiconductor chip die and footprints of the plurality of core balls are within a footprint of the second semiconductor chip die.