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    Memory device including predecoder and operating method thereof
    1.
    发明授权
    Memory device including predecoder and operating method thereof 有权

    公开(公告)号：US12112795B2

    公开(公告)日：2024-10-08

    申请号：US17565743

    申请日：2021-12-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyu Won Choi ,  Tae Min Choi ,  Hyeong Cheol Kim ,  Chan Ho Lee

    IPC: G11C11/413 ,  G11C11/418 ,  H03K19/017

    CPC classification number: G11C11/418 ,  G11C11/413 ,  H03K19/01742

    Abstract: A memory device and operating method of the memory device are provided. The memory device comprises a memory cell storing data based on a first voltage, a row decoder selecting a wordline of the memory cell based on the first voltage, and a wordline predecoder configured to generate a “predec” signal, which is for generating a wordline voltage to be provided to the row decoder. The wordline predecoder is driven by the first voltage and a second voltage, which is different from the first voltage, receives a row address signal, associated with selecting the wordline, and an internal clock signal associated with adjusting operating timings of elements included in the memory device. The wordline predecoder performs a NAND operation on the row address signal and the internal clock signal, and provides the “predec” signal generated based on a result of the NAND operation to the row decoder.

    Pseudo dual port memory devices
    2.
    发明授权
    Pseudo dual port memory devices 有权

    公开(公告)号：US11923035B2

    公开(公告)日：2024-03-05

    申请号：US17668760

    申请日：2022-02-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chan Ho Lee ,  Tae Min Choi ,  Jeong Kyun Kim ,  Hyeong Cheol Kim ,  Suk Youn ,  Ju Chang Lee ,  Kyu Won Choi

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

    CPC classification number: G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12

    Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

    Memory device with real-time monitoring
    4.
    发明授权
    Memory device with real-time monitoring 有权

    公开(公告)号：US11960319B2

    公开(公告)日：2024-04-16

    申请号：US17678117

    申请日：2022-02-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tae Min Choi ,  Chan Ho Lee ,  Jung Hak Song ,  Ju Chang Lee ,  Woo Jin Jung

    IPC: G06F1/06 ,  G11C11/41

    CPC classification number: G06F1/06 ,  G11C11/41

    Abstract: A memory device is provided. The memory device comprises an internal clock generator configured to receive an external clock signal from a host and generate an internal clock signal in accordance with a chip enable signal, an internal enable signal generator configured to operate based on the internal clock signal and receive an external enable signal from the host and generate an internal enable signal, and a monitoring signal generator configured to output a monitoring signal that is generated based on at least one of the internal clock signal or the internal enable signal to the host.

    PSEUDO DUAL PORT MEMORY DEVICES
    5.
    发明公开
    PSEUDO DUAL PORT MEMORY DEVICES 审中-公开

    公开(公告)号：US20240185896A1

    公开(公告)日：2024-06-06

    申请号：US18441089

    申请日：2024-02-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chan Ho Lee ,  Tae Min Choi ,  Jeong Kyun Kim ,  Hyeong Cheol Kim ,  Suk Youn ,  Ju Chang Lee ,  Kyu Won Choi

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

    CPC classification number: G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12

    Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

    PSEUDO DUAL PORT MEMORY DEVICES
    6.
    发明申请
    PSEUDO DUAL PORT MEMORY DEVICES 有权

    公开(公告)号：US20220366944A1

    公开(公告)日：2022-11-17

    申请号：US17668760

    申请日：2022-02-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chan Ho Lee ,  Tae Min Choi ,  Jeong Kyun Kim ,  Hyeong Cheol Kim ,  Suk Youn ,  Ju Chang Lee ,  Kyu Won Choi

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

    Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

    MEMORY DEVICE
    8.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20220350362A1

    公开(公告)日：2022-11-03

    申请号：US17678117

    申请日：2022-02-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tae Min Choi ,  Chan Ho Lee ,  Jung Hak Song ,  Ju Chang Lee ,  Woo Jin Jung

    IPC: G06F1/06

    Abstract: A memory device is provided. The memory device comprises an internal clock generator configured to receive an external clock signal from a host and generate an internal clock signal in accordance with a chip enable signal, an internal enable signal generator configured to operate based on the internal clock signal and receive an external enable signal from the host and generate an internal enable signal, and a monitoring signal generator configured to output a monitoring signal that is generated based on at least one of the internal clock signal or the internal enable signal to the host.

    Semiconductor devices
    9.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11437320B2

    公开(公告)日：2022-09-06

    申请号：US16835557

    申请日：2020-03-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Suk Youn ,  Chan Ho Lee ,  Uk Rae Cho ,  Woo jin Jung ,  Kyu Won Choi

    IPC: G11C7/18 ,  H01L23/528 ,  H01L27/105 ,  H01L29/06 ,  G11C8/14 ,  H01L27/088 ,  H01L29/78

    Abstract: A semiconductor device includes a substrate including a first cell region, a second cell region adjacent to the first cell region in a first direction, and a comparison region adjacent the first and second cell regions in a second direction, a bit line in a first metal level on the substrate and extending in the first direction, and a first ground rail in a second metal level different from the first metal level. The first ground rail comprises a first sub-ground rail extending in the second direction on the first cell region, a second sub-ground rail extending in the second direction on the second cell region, a third sub-ground rail connecting the first sub-ground rail to the second sub-ground rail on the first and second cell regions, and a fourth sub-ground rail that branches off from the third sub-ground rail and extends in the second direction.

    SEMICONDUCTOR DEVICES
    10.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210028109A1

    公开(公告)日：2021-01-28

    申请号：US16835557

    申请日：2020-03-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Suk Youn ,  Chan Ho Lee ,  Uk Rae Cho ,  Woo jin Jung ,  Kyu Won Choi

    IPC: H01L23/528 ,  H01L27/105 ,  H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  G11C7/18 ,  G11C8/14

    Abstract: A semiconductor device includes a substrate including a first cell region, a second cell region adjacent to the first cell region in a first direction, and a comparison region adjacent the first and second cell regions in a second direction, a bit line in a first metal level on the substrate and extending in the first direction, and a first ground rail in a second metal level different from the first metal level. The first ground rail comprises a first sub-ground rail extending in the second direction on the first cell region, a second sub-ground rail extending in the second direction on the second cell region, a third sub-ground rail connecting the first sub-ground rail to the second sub-ground rail on the first and second cell regions, and a fourth sub-ground rail that branches off from the third sub-ground rail and extends in the second direction.

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