公开(公告)号：US20180166334A1

公开(公告)日：2018-06-14

申请号：US15668029

申请日：2017-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Rak Hwan KIM ,  Byung Hee KIM ,  Sang Bom KANG ,  Jong Jin LEE ,  Eun Ji JUNG

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/485

CPC classification number: H01L21/76846 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact electrically connects the lower layer and the upper layer, a capping pattern wrapping around the contact and covering an upper surface of the contact, a barrier layer wrapping around the capping pattern and covering a lower surface of the capping pattern and a lower surface of the contact, and an interlayer insulating layer between the lower layer and the upper layer, the interlayer insulating layer wrapping around the barrier layer and exposing an upper surface of the capping pattern, wherein the capping pattern includes a material having an etching selectivity with respect to an oxide.

公开(公告)号：US20180076140A1

公开(公告)日：2018-03-15

申请号：US15480055

申请日：2017-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Hee KIM ,  Thomas Oszinda ,  Deok Young Jung ,  Jong Min Baek ,  Tae Jin Yim

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5329 ,  H01L21/76802 ,  H01L21/76822 ,  H01L21/76829 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: Semiconductor devices including an interconnection structure are provided. The devices may include an etch stop layer on a lower structure including a contact structure, a buffer layer on the etch stop layer, an intermetal insulating layer including a low-k dielectric material on the buffer layer. The intermetal insulating layer may include a first region having a first dielectric constant and a second region having a second dielectric constant different from the first dielectric constant. The device may also include interconnection structure including a plug portion electrically connected to the contact structure and an interconnection portion on the plug portion. The plug portion may include a first portion extending through the etch stop layer and a second portion that is in the intermetal insulating layer and has a width greater than a width of the first portion. The interconnection portion may include opposing lateral surfaces surrounded by the intermetal insulating layer.

公开(公告)号：US20170213786A1

公开(公告)日：2017-07-27

申请号：US15333508

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon AHN ,  Tae Soo KIM ,  Jong Min BAEK ,  Woo Kyung YOU ,  Thomas OSZINDA ,  Byung Hee KIM ,  Nae In LEE

IPC: H01L23/498 ,  H01L23/535

CPC classification number: H01L23/53295 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.

公开(公告)号：US20190019759A1

公开(公告)日：2019-01-17

申请号：US16135234

申请日：2018-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hoon AHN ,  Tae Soo KIM ,  Jong Min BAEK ,  Woo Kyung YOU ,  Thomas OSZINDA ,  Byung Hee KIM ,  Nae In LEE

IPC: H01L23/532

Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.

公开(公告)号：US20170162431A1

公开(公告)日：2017-06-08

申请号：US15353984

申请日：2016-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon AHN ,  Jong Min BAEK ,  Myung Geun SONG ,  Woo Kyung YOU ,  Byung Kwon CHO ,  Byung Hee KIM ,  Na Ein LEE

IPC: H01L21/768 ,  H01L21/3205 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295

Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.

公开(公告)号：US20160293552A1

公开(公告)日：2016-10-06

申请号：US15048998

申请日：2016-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jin YIM ,  Sang-Hoon AHN ,  Thomas OSZINDA ,  Jong-Min BAEK ,  Byung Hee KIM ,  Nae-In LEE ,  Kee-Young JUN

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76867 ,  H01L23/5283 ,  H01L23/53295

Abstract: A semiconductor device includes an insulating interlayer on a first region of a substrate. The insulating interlayer has a recess therein and includes a low-k material having porosity. A damage curing layer is formed on an inner surface of the recess. A barrier pattern is formed on the damage curing layer. A copper structure fills the recess and is disposed on the barrier pattern. The copper structure includes a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern. A diffusion of metal in a wiring structure of the semiconductor device may be prevented, and thus a resistance of the wiring structure may decrease.

Abstract translation: 半导体器件包括在衬底的第一区域上的绝缘中间层。 绝缘中间层具有凹部，并且包括具有多孔性的低k材料。 在凹部的内表面上形成损伤固化层。 在损伤固化层上形成阻挡图案。 铜结构填充凹部并设置在阻挡图案上。 铜结构包括铜图案和覆盖铜图案表面的铜 - 锰覆盖图案。 可以防止金属在半导体器件的布线结构中的扩散，因此布线结构的电阻可能降低。

公开(公告)号：US20200251376A1

公开(公告)日：2020-08-06

申请号：US16854979

申请日：2020-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyu Hee HAN ,  Jong Min BAEK ,  Viet Ha NGUYEN ,  Woo Kyung YOU ,  Sang Shin JANG ,  Byung Hee KIM

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311

Abstract: A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.

公开(公告)号：US20180102280A1

公开(公告)日：2018-04-12

申请号：US15636889

申请日：2017-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Viet Ha NGUYEN ,  Nae In LEE ,  Thomas OSZINDA ,  Byung Hee KIM ,  Jong Min BAEK ,  Tae Jin YIM

IPC: H01L21/768

CPC classification number: H01L21/76826 ,  H01L21/76814 ,  H01L21/76877 ,  H01L21/76888

Abstract: Methods for fabricating semiconductor devices may provide enhanced performance and reliability by recovering quality of a low-k insulating film damaged by a plasma process. A method may include forming a first interlayer insulating film having a trench therein on a substrate, filling at least a portion of the trench with a metal wiring region, exposing a surface of the metal wiring region and a surface of the first interlayer insulating film to a plasma in a first surface treatment process, then exposing the surface of the first interlayer insulating film to a recovery gas containing a methyl group (—CH3) in a second surface treatment process, and then forming an etch stop layer on the metal wiring region and the first interlayer insulating film.

公开(公告)号：US20180096880A1

公开(公告)日：2018-04-05

申请号：US15612102

申请日：2017-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyu Hee HAN ,  Jong Min BAEK ,  Viet Ha NGUYEN ,  Woo Kyung YOU ,  Sang Shin JANG ,  Byung Hee KIM

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.

公开(公告)号：US20180053685A1

公开(公告)日：2018-02-22

申请号：US15802724

申请日：2017-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon AHN ,  Jong Min BAEK ,  Myung Geun SONG ,  Woo Kyung YOU ,  Byung Kwon CHO ,  Byung Hee KIM ,  Na Ein LEE

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/311

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295

Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.