公开(公告)号：US20170213786A1

公开(公告)日：2017-07-27

申请号：US15333508

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon AHN ,  Tae Soo KIM ,  Jong Min BAEK ,  Woo Kyung YOU ,  Thomas OSZINDA ,  Byung Hee KIM ,  Nae In LEE

IPC: H01L23/498 ,  H01L23/535

CPC classification number: H01L23/53295 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.

公开(公告)号：US20190304903A1

公开(公告)日：2019-10-03

申请号：US16446226

申请日：2019-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Kyung YOU ,  Eui Bok LEE ,  Jong Min BAEK ,  Su Hyun BARK ,  Jang Ho LEE ,  Sang Hoon AHN ,  Hyeok Sang OH

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.

公开(公告)号：US20190244896A1

公开(公告)日：2019-08-08

申请号：US16008319

申请日：2018-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok LEE ,  Jong Min BAEK ,  Sang Hoon AHN ,  Hyeok Sang OH

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532

Abstract: A semiconductor device includes a lower insulating layer disposed on a substrate. A conductive pattern is formed in the lower insulating layer. A middle insulating layer is disposed on the lower insulating layer and the conductive pattern. A via control region is formed in the middle insulating layer. An upper insulating layer is disposed on the middle insulating layer and the via control region. A via plug is formed to pass through the via control region and to be connected to the conductive pattern. The via control region has a lower etch rate than the middle insulating layer.

公开(公告)号：US20180053685A1

公开(公告)日：2018-02-22

申请号：US15802724

申请日：2017-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon AHN ,  Jong Min BAEK ,  Myung Geun SONG ,  Woo Kyung YOU ,  Byung Kwon CHO ,  Byung Hee KIM ,  Na Ein LEE

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/311

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295

Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.

公开(公告)号：US20170194535A1

公开(公告)日：2017-07-06

申请号：US15237806

申请日：2016-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Won PARK ,  Woon Seok KIM ,  Sang Hoon AHN ,  Ji Ho YOU ,  Chul Soo YOON

IPC: H01L33/50 ,  F21V8/00 ,  G02F1/1335 ,  H01L33/56

CPC classification number: H01L33/504 ,  G02B6/0015 ,  G02F1/133514 ,  G02F1/133603 ,  G02F2001/133614 ,  G02F2202/36 ,  H01L33/507 ,  H01L33/56 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A white light emitting device includes a blue light emitting diode emitting first light having a dominant wavelength in a range of 440 nm to 460 nm, a quantum dot disposed on a path of the emitted first light and converting a first portion of the emitted first light into green light, and a fluoride phosphor disposed on the path of the emitted first light and converting a second portion of the emitted first light into red light. The quantum dot includes a core formed of a group III-V compound and a shell formed of a group II-VI compound, and the fluoride phosphor is represented by empirical formula AxMFy:Mn4+, A being at least one selected from Li, Na, K, Rb, and Cs, M being at least one selected from Si, Ti, Zr, Hf, Ge, and Sn, and the empirical formula satisfying 2≦x≦3 and 4≦y≦7.

公开(公告)号：US20190181088A1

公开(公告)日：2019-06-13

申请号：US16039838

申请日：2018-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Deok Young JUNG ,  Sang Bom KANG ,  Doo-Hwan PARK ,  Jong Min BAEK ,  Sang Hoon AHN ,  Hyeok Sang OH ,  Woo Kyung YOU

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer. The first insulating film and the second insulating film may be sequentially stacked on the substrate in a vertical direction, and a longest vertical distance between an upper surface of the lower metal layer and the substrate may be less than a longest vertical distance between the upper surface of the second insulating film and the substrate.

公开(公告)号：US20190148289A1

公开(公告)日：2019-05-16

申请号：US15987211

申请日：2018-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon Seok SEO ,  Jong Min BAEK ,  Su Hyun BARK ,  Sang Hoon AHN ,  Hyeok Sang OH ,  Eui Bok LEE

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.

公开(公告)号：US20190043803A1

公开(公告)日：2019-02-07

申请号：US15840128

申请日：2017-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Kyung YOU ,  Eui Bok LEE ,  Jong Min BAEK ,  Su Hyun BARK ,  Jang Ho LEE ,  Sang Hoon AHN ,  Hyeok Sang OH

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.

公开(公告)号：US20190019759A1

公开(公告)日：2019-01-17

申请号：US16135234

申请日：2018-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hoon AHN ,  Tae Soo KIM ,  Jong Min BAEK ,  Woo Kyung YOU ,  Thomas OSZINDA ,  Byung Hee KIM ,  Nae In LEE

IPC: H01L23/532

Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.

公开(公告)号：US20170162431A1

公开(公告)日：2017-06-08

申请号：US15353984

申请日：2016-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon AHN ,  Jong Min BAEK ,  Myung Geun SONG ,  Woo Kyung YOU ,  Byung Kwon CHO ,  Byung Hee KIM ,  Na Ein LEE

IPC: H01L21/768 ,  H01L21/3205 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295

Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.