公开(公告)号：US20200075324A1

公开(公告)日：2020-03-05

申请号：US16385441

申请日：2019-04-16

申请人： Samsung Electronics Co., Ltd.

发明人： Kaoru YAMAMOTO ,  Chang-Hyun KIM ,  Hyun-Jae SONG ,  Keun-Wook SHIN ,  Hyeon-Jin SHIN ,  Sung-Joo AN ,  Chang-Seok LEE ,  Kee-Young JUN ,  Geun-O JEONG ,  Jang-Hee LEE

IPC分类号： H01L21/02 ,  H01L21/67 ,  H01J37/32

摘要： In a plasma deposition method, a substrate is loaded onto a substrate stage within a chamber. A first plasma is generated at a region separated from the substrate by a first distance. A first process gas is supplied to the first plasma region to perform a pre-treatment process on the substrate. A second plasma is generated at a region separated from the substrate by a second distance different from the first distance. A second process gas is supplied to the second plasma region to perform a deposition process on the substrate.

公开(公告)号：US20160293552A1

公开(公告)日：2016-10-06

申请号：US15048998

申请日：2016-02-19

申请人： Samsung Electronics Co., Ltd.

发明人： Tae-Jin YIM ,  Sang-Hoon AHN ,  Thomas OSZINDA ,  Jong-Min BAEK ,  Byung Hee KIM ,  Nae-In LEE ,  Kee-Young JUN

IPC分类号： H01L23/532 ,  H01L23/528

CPC分类号： H01L23/53238 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76867 ,  H01L23/5283 ,  H01L23/53295

摘要： A semiconductor device includes an insulating interlayer on a first region of a substrate. The insulating interlayer has a recess therein and includes a low-k material having porosity. A damage curing layer is formed on an inner surface of the recess. A barrier pattern is formed on the damage curing layer. A copper structure fills the recess and is disposed on the barrier pattern. The copper structure includes a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern. A diffusion of metal in a wiring structure of the semiconductor device may be prevented, and thus a resistance of the wiring structure may decrease.

摘要翻译： 半导体器件包括在衬底的第一区域上的绝缘中间层。 绝缘中间层具有凹部，并且包括具有多孔性的低k材料。 在凹部的内表面上形成损伤固化层。 在损伤固化层上形成阻挡图案。 铜结构填充凹部并设置在阻挡图案上。 铜结构包括铜图案和覆盖铜图案表面的铜 - 锰覆盖图案。 可以防止金属在半导体器件的布线结构中的扩散，因此布线结构的电阻可能降低。

公开(公告)号：US20160211211A1

公开(公告)日：2016-07-21

申请号：US14984085

申请日：2015-12-30

申请人： Samsung Electronics Co., Ltd.

发明人： Tae-Jin YIM ,  Woo-Kyung YOU ,  Jong-Min BAEK ,  Sang-Hoon AHN ,  Thomas OSZINDA ,  Kee-Young JUN

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L23/53295 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided. The semiconductor device includes a first porous interlayer insulating film having a low dielectric constant and including a first region and a second region, a second interlayer insulating film formed on the first interlayer insulating film in the first region, a plurality of first conductive patterns formed in the second interlayer insulating film such that the plurality of first conductive patterns are spaced apart from each other, at least one second conductive pattern formed in the first interlayer insulating film in the second region and air gaps disposed at lateral sides of the plurality of first conductive patterns.

摘要翻译： 提供半导体器件。 半导体器件包括具有低介电常数并且包括第一区域和第二区域的第一多孔层间绝缘膜，形成在第一区域中的第一层间绝缘膜上的第二层间绝缘膜，形成在第一区域中的多个第一导电图案 所述第二层间绝缘膜使得所述多个第一导电图案彼此间隔开，形成在所述第二区域中的所述第一层间绝缘膜中的至少一个第二导电图案和设置在所述多个第一导电性 模式。