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    Substrate processing apparatus and method of cleaning the same
    1.
    发明授权
    Substrate processing apparatus and method of cleaning the same 有权

    公开(公告)号：US10822694B2

    公开(公告)日：2020-11-03

    申请号：US16104311

    申请日：2018-08-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sukjin Chung ,  Bongjin Kuh ,  Kook Tae Kim ,  In-Sun Yi ,  Soojin Hong

    IPC: C23C16/44 ,  C23C16/458 ,  C23C16/455

    Abstract: Disclosed are a substrate processing apparatus and a method of cleaning the apparatus. The apparatus includes a process chamber, a support unit in the process chamber and configured to support a substrate, and a gas injection unit in the process chamber. The gas injection unit includes a first injection portion configured to inject a source gas, a second injection portion facing the first injection portion and configured to inject a reaction gas that reacts with the source gas, and a third injection portion configured to inject a cleaning gas that removes a reactant produced from the source gas and the reaction gas.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20240395615A1

    公开(公告)日：2024-11-28

    申请号：US18631548

    申请日：2024-04-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seokwon Kim ,  Bongjin Kuh ,  Sukhoon Kim ,  Jiho Park ,  Sanghyeok Yu ,  Yongho Ha ,  Musarrat Hasan

    IPC: H01L21/768 ,  C23C16/34 ,  C23C16/505

    Abstract: A method of manufacturing a semiconductor device includes forming a substrate including a structure having a first region and a contact hole exposing the first region, loading the substrate into a process chamber, repeatedly performing two or more times, a deposition process that includes repeatedly applying radio frequency (RF) plasma power to a process gas for a first time duration and not applying the RF plasma power to the process gas for a second time duration, and a soak process that does not use plasma, at a metal-semiconductor compound formation temperature or higher, within the process chamber, and thereby forming a metal-semiconductor compound layer on the first region, a sidewall material layer on a sidewall of the contact hole, and an upper material layer on the structure, performing a removal process of removing at least a portion of the sidewall material layer in the process chamber, and unloading the substrate from the process chamber after performing the removal process.

    Semiconductor device and method of fabricating the same
    3.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09443932B2

    公开(公告)日：2016-09-13

    申请号：US14330777

    申请日：2014-07-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ki-Chul Kim ,  Joonghan Shin ,  Bongjin Kuh ,  Taegon Kim ,  Hanmei Choi

    IPC: H01L21/70 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238

    CPC classification number: H01L29/0696 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1211

    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a plurality of unit cells provided on a semiconductor substrate. Each of the unit cells may include a buried insulating pattern buried in the semiconductor substrate, a first active pattern provided on the buried insulating pattern, and a second active pattern provided on the buried insulating pattern and spaced apart from the first active pattern. The buried insulating pattern may define a unit cell region, in which each of the unit cells may be disposed.

    Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括设置在半导体衬底上的多个单元电池。 每个单电池可以包括埋在半导体衬底中的掩埋绝缘图案，设置在掩埋绝缘图案上的第一有源图案和设置在掩埋绝缘图案上并与第一有源图案间隔开的第二有源图案。 埋置的绝缘图案可以限定单位单元区域，其中可以布置每个单位单元。

    Semiconductor device with an epitaxial layer and method of fabricating the same
    4.
    发明授权
    Semiconductor device with an epitaxial layer and method of fabricating the same 有权
    具有外延层的半导体器件及其制造方法

    公开(公告)号：US09537029B2

    公开(公告)日：2017-01-03

    申请号：US14582294

    申请日：2014-12-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Beom Seok Kim ,  Bongjin Kuh ,  Jongsung Lim ,  Hanmei Choi

    IPC: H01L21/02 ,  H01L31/0352 ,  H01L31/18

    CPC classification number: H01L31/03529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26513 ,  H01L31/1804 ,  H01L31/1864 ,  Y02P70/521

    Abstract: A semiconductor device includes a first semiconductor layer including a recess region and protrusions defined by the recessed region, first insulating patterns provided on the protrusions and extending to sidewalls of the protrusions, and a second semiconductor layer to fill the recess region and cover the first insulating patterns. The protrusions includes a first group of protrusions spaced apart from each other in a first direction to constitute a row and a second group of protrusions spaced from the first group of protrusions in a second direction intersecting the first direction and spaced from each other in the first direction to constitute a row. The second group of protrusions are shifted from the first group of protrusions in the first direction.

    Abstract translation: 半导体器件包括：第一半导体层，包括凹陷区域和由凹陷区域限定的突起;设置在突起上并延伸到突起侧壁的第一绝缘图案;以及第二半导体层，用于填充凹陷区域并覆盖第一绝缘体 模式。 突起包括在第一方向上彼此间隔开的第一组突起，以构成一排，并且在与第一方向相交的第二方向上与第一组突起间隔开的第二组突起在第一方向上彼此间隔开 方向构成一排。 第二组突起在第一方向从第一组突起移位。

    FERROELECTRIC MEMORY DEVICE
    5.
    发明公开
    FERROELECTRIC MEMORY DEVICE 审中-公开

    公开(公告)号：US20230165012A1

    公开(公告)日：2023-05-25

    申请号：US18049366

    申请日：2022-10-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Gabjin Nam ,  Bongjin Kuh ,  Musarrat Hasan ,  Geonju Park ,  Yongho Ha

    IPC: H01L27/1159

    CPC classification number: H01L27/1159

    Abstract: A ferroelectric memory device according to the inventive concept includes a substrate having source/drain regions, an interface layer on the substrate, a high dielectric layer on the interface layer, a ferroelectric layer on the high dielectric layer, and a gate electrode layer on the ferroelectric layer. The high dielectric layer and the ferroelectric layer have phases of different crystal structures.

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