公开(公告)号：US20240314930A1

公开(公告)日：2024-09-19

申请号：US18490678

申请日：2023-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alan GARA ,  Young-Jun HONG ,  Eric Richard BORCH ,  Casey THIELEN

IPC: H05K1/14 ,  H04L49/00 ,  H05K7/14

CPC classification number: H05K1/14 ,  H04L49/70 ,  H05K7/1445 ,  H05K2201/044

Abstract: A computing system with connecting boards. In some embodiments, the computing system includes a first compute board, a second compute board, and a first connecting board connected to the first compute board and to the second compute board. The first compute board and the second compute board may include a plurality of compute elements. The first compute board, the second compute board, and the first connecting board may include a first plurality of switches including a first switch connected to a first compute element of the plurality of compute elements and a second switch connected to a second compute element of the plurality of compute elements. The first connecting board may include a first conductor, the first conductor being a conductor of a first data connection between the first switch and the second switch.

公开(公告)号：US20240311323A1

公开(公告)日：2024-09-19

申请号：US18232819

申请日：2023-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eric Richard BORCH ,  Casey Glenn THIELEN ,  Alan GARA ,  Young Jun HONG

IPC: G06F13/40 ,  G06F11/34

CPC classification number: G06F13/4022 ,  G06F11/3495

Abstract: Embodiments disclose methods, systems and devices including a plurality of connectors, a plurality of switches, and a plurality of compute elements. Each of the plurality of compute elements may be connected to each of the plurality of switches. In some embodiments, a first subset of the plurality of switches may be directly connected to a first subset of the plurality of the connectors in a fanout mechanism, and a second subset of the plurality of switches may be directly connected to a second subset of the plurality of the connectors in a similar fanout mechanism.

公开(公告)号：US20240311308A1

公开(公告)日：2024-09-19

申请号：US18534560

申请日：2023-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Arun Francis RODRIGUES ,  Alan GARA ,  Douglas JOSEPH ,  Jai DAYAL ,  David LOMBARD ,  Manisha GAJBE ,  Andrew TAUFERNER ,  Casey THIELEN ,  Ping ZOU ,  Samantika SURY ,  Eric BORCH ,  Zaid MCKIE KRISBERG ,  Robert WISNIEWSKI

IPC: G06F12/0891 ,  G06F11/07 ,  G06F12/084

CPC classification number: G06F12/0891 ,  G06F11/0772 ,  G06F12/084

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, the method includes: determining that a first data value in a cache is a global data value; setting a first flag to indicate that the first data value is a global data value; and selectively invalidating one or more portions of the cache, wherein the selective invalidating of the cache includes: determining, based on the first flag, that the first data value is a global data value; and based on the determining, invalidating the first data value.

公开(公告)号：US20250139012A1

公开(公告)日：2025-05-01

申请号：US19011544

申请日：2025-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alan GARA ,  Douglas JOSEPH ,  Arun RODRIGUES ,  Samantika SURY ,  Rolf RIESEN ,  Robert WISNIEWSKI

IPC: G06F12/0891 ,  G06F12/084 ,  G06F13/16

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes: executing, by a first node of a plurality of nodes, a global clean, the executing including: determining that a first cached value in a cache of the first node is a modified cached copy of data in a shared memory, the shared memory being shared by the nodes; and in response to determining that the first cached value is a modified cached copy of data in the shared memory, writing back the first cached value to the shared memory.

公开(公告)号：US20240311315A1

公开(公告)日：2024-09-19

申请号：US18483486

申请日：2023-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alan GARA ,  Douglas JOSEPH ,  Arun RODRIGUES ,  Samantika SURY ,  Rolf RIESEN ,  Robert WISNIEWSKI

IPC: G06F13/16 ,  G06F12/0808

CPC classification number: G06F13/1663 ,  G06F12/0808 ,  G06F13/1689

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes: reading, by a first node of a plurality of nodes, from a shared memory shared by the nodes, a first data value; modifying, by the first node, the first data value; storing, by the first node, the modified first data value in a cache of the first node; initiating, by the first node, a global synchronization command; and in response to the initiating, by the first node, of the global synchronization command: indicating, by the first node, that the first node has completed a time step synchronization.

公开(公告)号：US20230254253A1

公开(公告)日：2023-08-10

申请号：US18101732

申请日：2023-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Jun HONG ,  Alan GARA ,  Wonseok LEE ,  Wonyong LEE ,  Wooseok CHANG

IPC: H04L47/10 ,  G06F13/40

CPC classification number: H04L47/18 ,  G06F13/4068

Abstract: Message splitting and aggregation in a multi-stage electrical interconnection network are disclosed. A method of operating an electronic device comprised of computing devices, includes splitting, into segments, a message to be transmitted from a first of the computing devices, transmitting the segments to a second of the computing devices through a multi-channel that is based on an electrical connection between the first computing device and a plurality of switches, wherein the multi-channel includes channels respectively including electrical connections, the electrical connections connecting the first computing device with the second computing device, and reconstructing the message by aggregating the segments in the second computing device, wherein a bandwidth of the multi-channel transmitting the segments is greater than a maximum bandwidth of a single electrical connection of the electrical connections.

公开(公告)号：US20250139010A1

公开(公告)日：2025-05-01

申请号：US19011539

申请日：2025-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alan GARA ,  Douglas JOSEPH ,  Arun RODRIGUES ,  Samantika SURY ,  Rolf RIESEN ,  Robert WISNIEWSKI

IPC: G06F12/084 ,  G06F12/0891

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes: executing, by a first node of a plurality of nodes, a global load from a first address of a shared memory, the shared memory being shared by the nodes, the first address being an address within a shared memory section of a second node, the first address being cached in a first cache of the first node, the executing including: fetching a value stored in the shared memory, at the first address.

公开(公告)号：US20250139007A1

公开(公告)日：2025-05-01

申请号：US19011563

申请日：2025-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alan GARA ,  Douglas JOSEPH ,  Arun RODRIGUES ,  Samantika SURY ,  Rolf RIESEN ,  Robert WISNIEWSKI

IPC: G06F12/0808 ,  G06F11/07 ,  G06F12/0864 ,  G06F13/16

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes writing, during each of a sequence of time steps, by each node of a plurality of nodes, to a shared memory, the shared memory being shared by the nodes, wherein: each of the nodes includes a hardware-maintained coherence domain and is connected to the other nodes, and each of the nodes includes a respective portion of the shared memory.

公开(公告)号：US20230369171A1

公开(公告)日：2023-11-16

申请号：US18358386

申请日：2023-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Jun HONG ,  Wonyong LEE ,  Alan GARA ,  Se Hyun YANG ,  Wooseok CHANG

IPC: H01L23/48 ,  H01L23/498 ,  G06F13/40 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L23/481 ,  H10B80/00 ,  H01L23/49838 ,  H01L23/49833 ,  G06F13/4022 ,  H01L25/16 ,  H01L23/49816 ,  H01L24/16 ,  H01L2924/1511 ,  H01L2924/1431 ,  H01L2224/16238 ,  H01L2224/16148 ,  H01L2924/14335 ,  H01L2224/16227 ,  H01L2924/1436 ,  H01L2924/1432

Abstract: A computing device includes: a processor; a memory stack in which memories connected to the processor are stacked; and a substrate disposed under the processor, wherein a network bandwidth between the processor and the substrate is five or less times a memory bandwidth between the processor and the memory stack.

公开(公告)号：US20230253294A1

公开(公告)日：2023-08-10

申请号：US18101565

申请日：2023-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonyong LEE ,  Alan GARA ,  Se Hyun YANG ,  Young Jun HONG ,  Wooseok CHANG

IPC: H01L23/48 ,  G06F13/40 ,  H01L25/16 ,  H10B80/00 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/481 ,  G06F13/4022 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/16 ,  H10B80/00 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1511 ,  H01L2924/14335

Abstract: A computing device includes: a processor; a memory stack in which memories connected to the processor are stacked; and a substrate disposed under the processor, wherein a network bandwidth between the processor and the substrate is five or less times a memory bandwidth between the processor and the memory stack.