公开(公告)号：US20250117337A1

公开(公告)日：2025-04-10

申请号：US18587940

申请日：2024-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aditya Madhusudan DESHPANDE ,  Douglas JOSEPH ,  Manisha GAJBE ,  Arun RODRIGUES

IPC: G06F12/1027

Abstract: Provided are systems, methods, and apparatuses for transferring computational tasks. In one or more examples, the systems, methods, and apparatuses include a first host configured to detect a trigger to offload instruction code from the first host to a second host; identify, based on the trigger, an address translation binding for the instruction code and an address translation binding for application data associated with the instruction code; copy the address translation binding for the instruction code and the address translation binding for the application data to a memory; and transfer control of execution of the instruction code to the second host based on the copying.

公开(公告)号：US20250139010A1

公开(公告)日：2025-05-01

申请号：US19011539

申请日：2025-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alan GARA ,  Douglas JOSEPH ,  Arun RODRIGUES ,  Samantika SURY ,  Rolf RIESEN ,  Robert WISNIEWSKI

IPC: G06F12/084 ,  G06F12/0891

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes: executing, by a first node of a plurality of nodes, a global load from a first address of a shared memory, the shared memory being shared by the nodes, the first address being an address within a shared memory section of a second node, the first address being cached in a first cache of the first node, the executing including: fetching a value stored in the shared memory, at the first address.

公开(公告)号：US20250139007A1

公开(公告)日：2025-05-01

申请号：US19011563

申请日：2025-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alan GARA ,  Douglas JOSEPH ,  Arun RODRIGUES ,  Samantika SURY ,  Rolf RIESEN ,  Robert WISNIEWSKI

IPC: G06F12/0808 ,  G06F11/07 ,  G06F12/0864 ,  G06F13/16

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes writing, during each of a sequence of time steps, by each node of a plurality of nodes, to a shared memory, the shared memory being shared by the nodes, wherein: each of the nodes includes a hardware-maintained coherence domain and is connected to the other nodes, and each of the nodes includes a respective portion of the shared memory.

公开(公告)号：US20250139012A1

公开(公告)日：2025-05-01

申请号：US19011544

申请日：2025-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alan GARA ,  Douglas JOSEPH ,  Arun RODRIGUES ,  Samantika SURY ,  Rolf RIESEN ,  Robert WISNIEWSKI

IPC: G06F12/0891 ,  G06F12/084 ,  G06F13/16

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes: executing, by a first node of a plurality of nodes, a global clean, the executing including: determining that a first cached value in a cache of the first node is a modified cached copy of data in a shared memory, the shared memory being shared by the nodes; and in response to determining that the first cached value is a modified cached copy of data in the shared memory, writing back the first cached value to the shared memory.

公开(公告)号：US20250139006A1

公开(公告)日：2025-05-01

申请号：US18741764

申请日：2024-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aditya Madhusudan DESHPANDE ,  Douglas JOSEPH ,  Arun RODRIGUES ,  Manisha GAJBE

IPC: G06F12/0806

Abstract: In some aspects, the techniques described herein relate to a device including a storage media and a processor including a cache hierarchy including a first cache, a second cache, and a third cache, wherein the first cache and the third cache are organized in an inclusive cache hierarchy, and wherein the second cache is an exclusive cache to the inclusive cache hierarchy; and a cache directory, wherein the cache directory corresponds to the first cache, second cache, and third cache. In some aspects, the processor performs operations including searching the first cache for data, searching the second cache for the data, and searching the cache directory for the data. In some aspects, searching the cache directory includes determining that the data is located in the cache directory and determining a location of the data in the cache hierarchy based on an entry in the cache directory.

公开(公告)号：US20240311315A1

公开(公告)日：2024-09-19

申请号：US18483486

申请日：2023-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alan GARA ,  Douglas JOSEPH ,  Arun RODRIGUES ,  Samantika SURY ,  Rolf RIESEN ,  Robert WISNIEWSKI

IPC: G06F13/16 ,  G06F12/0808

CPC classification number: G06F13/1663 ,  G06F12/0808 ,  G06F13/1689

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes: reading, by a first node of a plurality of nodes, from a shared memory shared by the nodes, a first data value; modifying, by the first node, the first data value; storing, by the first node, the modified first data value in a cache of the first node; initiating, by the first node, a global synchronization command; and in response to the initiating, by the first node, of the global synchronization command: indicating, by the first node, that the first node has completed a time step synchronization.