公开(公告)号：US20240311308A1

公开(公告)日：2024-09-19

申请号：US18534560

申请日：2023-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Arun Francis RODRIGUES ,  Alan GARA ,  Douglas JOSEPH ,  Jai DAYAL ,  David LOMBARD ,  Manisha GAJBE ,  Andrew TAUFERNER ,  Casey THIELEN ,  Ping ZOU ,  Samantika SURY ,  Eric BORCH ,  Zaid MCKIE KRISBERG ,  Robert WISNIEWSKI

IPC: G06F12/0891 ,  G06F11/07 ,  G06F12/084

CPC classification number: G06F12/0891 ,  G06F11/0772 ,  G06F12/084

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, the method includes: determining that a first data value in a cache is a global data value; setting a first flag to indicate that the first data value is a global data value; and selectively invalidating one or more portions of the cache, wherein the selective invalidating of the cache includes: determining, based on the first flag, that the first data value is a global data value; and based on the determining, invalidating the first data value.

公开(公告)号：US20250139012A1

公开(公告)日：2025-05-01

申请号：US19011544

申请日：2025-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alan GARA ,  Douglas JOSEPH ,  Arun RODRIGUES ,  Samantika SURY ,  Rolf RIESEN ,  Robert WISNIEWSKI

IPC: G06F12/0891 ,  G06F12/084 ,  G06F13/16

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes: executing, by a first node of a plurality of nodes, a global clean, the executing including: determining that a first cached value in a cache of the first node is a modified cached copy of data in a shared memory, the shared memory being shared by the nodes; and in response to determining that the first cached value is a modified cached copy of data in the shared memory, writing back the first cached value to the shared memory.

公开(公告)号：US20240311315A1

公开(公告)日：2024-09-19

申请号：US18483486

申请日：2023-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alan GARA ,  Douglas JOSEPH ,  Arun RODRIGUES ,  Samantika SURY ,  Rolf RIESEN ,  Robert WISNIEWSKI

IPC: G06F13/16 ,  G06F12/0808

CPC classification number: G06F13/1663 ,  G06F12/0808 ,  G06F13/1689

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes: reading, by a first node of a plurality of nodes, from a shared memory shared by the nodes, a first data value; modifying, by the first node, the first data value; storing, by the first node, the modified first data value in a cache of the first node; initiating, by the first node, a global synchronization command; and in response to the initiating, by the first node, of the global synchronization command: indicating, by the first node, that the first node has completed a time step synchronization.

公开(公告)号：US20250139010A1

公开(公告)日：2025-05-01

申请号：US19011539

申请日：2025-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alan GARA ,  Douglas JOSEPH ,  Arun RODRIGUES ,  Samantika SURY ,  Rolf RIESEN ,  Robert WISNIEWSKI

IPC: G06F12/084 ,  G06F12/0891

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes: executing, by a first node of a plurality of nodes, a global load from a first address of a shared memory, the shared memory being shared by the nodes, the first address being an address within a shared memory section of a second node, the first address being cached in a first cache of the first node, the executing including: fetching a value stored in the shared memory, at the first address.

公开(公告)号：US20250139007A1

公开(公告)日：2025-05-01

申请号：US19011563

申请日：2025-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alan GARA ,  Douglas JOSEPH ,  Arun RODRIGUES ,  Samantika SURY ,  Rolf RIESEN ,  Robert WISNIEWSKI

IPC: G06F12/0808 ,  G06F11/07 ,  G06F12/0864 ,  G06F13/16

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes writing, during each of a sequence of time steps, by each node of a plurality of nodes, to a shared memory, the shared memory being shared by the nodes, wherein: each of the nodes includes a hardware-maintained coherence domain and is connected to the other nodes, and each of the nodes includes a respective portion of the shared memory.

公开(公告)号：US20250044845A1

公开(公告)日：2025-02-06

申请号：US18527220

申请日：2023-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Praveen FRANCIS ,  Samantika SURY ,  Alfredo METERE ,  David LOMBARD

IPC: G06F1/26

Abstract: Provided are systems, methods, and apparatuses for obtaining first data of a power domain of a system on chip and second data of the power domain, predicting an expected power for the power domain based on the first data and the second data, and applying to the power domain a power level that is selected based on the expected power. The first data is utilization data. The second data is thermal data that includes at least one of a spatial thermal limit or a positional thermal limit of the power domain. The spatial thermal limit is based on at least one of a proximity of the power domain to a component outside the power domain or a power level of the component at a time when the expected power is calculated. The positional thermal limit is based on a location of the power domain on the system on chip.