知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.013 seconds)

    PRE-FETCHING ADDRESS TRANSLATION FOR COMPUTATION OFFLOADING
    5.
    发明申请
    PRE-FETCHING ADDRESS TRANSLATION FOR COMPUTATION OFFLOADING 有权

    公开(公告)号：US20250117337A1

    公开(公告)日：2025-04-10

    申请号：US18587940

    申请日：2024-02-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Aditya Madhusudan DESHPANDE ,  Douglas JOSEPH ,  Manisha GAJBE ,  Arun RODRIGUES

    IPC: G06F12/1027

    Abstract: Provided are systems, methods, and apparatuses for transferring computational tasks. In one or more examples, the systems, methods, and apparatuses include a first host configured to detect a trigger to offload instruction code from the first host to a second host; identify, based on the trigger, an address translation binding for the instruction code and an address translation binding for application data associated with the instruction code; copy the address translation binding for the instruction code and the address translation binding for the application data to a memory; and transfer control of execution of the instruction code to the second host based on the copying.

    METHOD FOR RANDOM NUMBER GENERATOR SEED CREATION USING UNINITIALIZED HARDWARE
    6.
    发明公开
    METHOD FOR RANDOM NUMBER GENERATOR SEED CREATION USING UNINITIALIZED HARDWARE 审中-公开

    公开(公告)号：US20240348434A1

    公开(公告)日：2024-10-17

    申请号：US18453305

    申请日：2023-08-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Andrew Thomas TAUFERNER ,  Douglas JOSEPH ,  Matthew WOLF

    IPC: H04L9/08

    CPC classification number: H04L9/0869

    Abstract: A computing device includes a memory and a processing device. The memory enters an uninitialized state in response to power being applied to the memory. The processing device is coupled to the memory, and is configured to select a portion of the memory in the uninitialized state to seed a random number generator process. The processing device may alternatively select an uninitialized state of the network hardware that is coupled to the processing device to seed a random number generator process. In one embodiment, the computing device is a compute node in a multi-node processing system, and the memory is a High-Bandwidth Memory.

    SYSTEMS, METHODS, AND APPARATUS FOR A CACHE DIRECTORY FOR A MULTI-LEVEL CACHE HIERARCHY
    8.
    发明申请
    SYSTEMS, METHODS, AND APPARATUS FOR A CACHE DIRECTORY FOR A MULTI-LEVEL CACHE HIERARCHY 有权

    公开(公告)号：US20250139006A1

    公开(公告)日：2025-05-01

    申请号：US18741764

    申请日：2024-06-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Aditya Madhusudan DESHPANDE ,  Douglas JOSEPH ,  Arun RODRIGUES ,  Manisha GAJBE

    IPC: G06F12/0806

    Abstract: In some aspects, the techniques described herein relate to a device including a storage media and a processor including a cache hierarchy including a first cache, a second cache, and a third cache, wherein the first cache and the third cache are organized in an inclusive cache hierarchy, and wherein the second cache is an exclusive cache to the inclusive cache hierarchy; and a cache directory, wherein the cache directory corresponds to the first cache, second cache, and third cache. In some aspects, the processor performs operations including searching the first cache for data, searching the second cache for the data, and searching the cache directory for the data. In some aspects, searching the cache directory includes determining that the data is located in the cache directory and determining a location of the data in the cache hierarchy based on an entry in the cache directory.

    SYSTEMS, METHODS, AND APPARATUS FOR REMOTE MEMORY ACCESS BY NODES
    9.
    发明公开
    SYSTEMS, METHODS, AND APPARATUS FOR REMOTE MEMORY ACCESS BY NODES 审中-公开

    公开(公告)号：US20240311316A1

    公开(公告)日：2024-09-19

    申请号：US18368556

    申请日：2023-09-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： David LOMBARD ,  Robert WISNIEWSKI ,  Douglas JOSEPH ,  Matthew WOLF ,  Jai DAYAL ,  James LOO ,  Andrew TAUFERNER ,  Rolf RIESEN

    IPC: G06F13/16 ,  G06F12/02

    CPC classification number: G06F13/1668 ,  G06F12/0292 ,  G06F13/1663

    Abstract: A computing node in a multi-node computing system includes a local memory, at least one processor, and an access library. The at least one processor runs an operating system that runs a distributed application in a virtual address space. The application includes a process that generates a first memory access request that includes a first virtual address. The access library is responsive to the first memory access request by: converting the first virtual address into a first physical address, accessing the local memory based on the first physical address including a first indication that the first memory access request is for the local memory, and accessing a global access tuple table based on the first physical address including a second indication that the first memory access request is for memory located on a second computing node of the multi-node computing system that is remotely located from the computing node.

Patent Agency Ranking