Abstract:
A display device includes a substrate including a display area and a non-display area surrounding the display area, a common voltage transmission line which is disposed in the non-display area and transmits a common voltage, a common voltage line disposed in the display area and connected with the common voltage transmission line, a common electrode disposed in the display area and the non-display area and connected with the common voltage line, a first pad disposed in the non-display area and connected with the common electrode, and a second pad disposed in the non-display area and connected with the common voltage transmission line.
Abstract:
A display device includes an auxiliary wire, a connection pattern, a light emitting layer, an upper common layer, and an upper electrode. The display device includes a sub-pixel region and a contact region. The auxiliary wire is disposed on a substrate in the contact region. The connection pattern is disposed on the auxiliary wire. The light emitting layer is disposed on the substrate in the sub-pixel region. The upper common layer is disposed on the light emitting layer and the connection pattern, and includes openings that expose the connection pattern. The upper electrode is disposed on the upper common layer and contacts the connection pattern by passing through the openings.
Abstract:
A flexible display device includes a flexible display panel, a first roller configured to wind the flexible display panel thereon, and a roller controller configured to rotate the first roller in a first direction and in a second direction opposite to the first direction, and to select from between the first direction and the second direction, such that the flexible display panel is wound selectively thereon in either of the first direction and the second direction.
Abstract:
A thin film transistor array panel includes an insulation substrate; a gate line and a data line on the insulation substrate; a first passivation layer on the gate line and the data line; an organic layer on the first passivation layer; a first electrode on the organic layer; a second passivation layer on the first electrode; and a second electrode on the second passivation layer. An edge of the organic layer is exposed by the first electrode.
Abstract:
A display device includes a first signal electrode configured to transfer a signal, a first insulating layer positioned on the first signal electrode, a first electrode positioned on the first insulating layer, a second insulating layer positioned on the first electrode, and a second electrode positioned on the second insulating layer, where a first contact hole exposing the first signal electrode is defined in the first insulating layer and the second insulating layer, the second electrode is connected with the first signal electrode through the first contact hole, and an opening including an edge side surrounding the first contact hole in a plan view is defined in the first electrode.
Abstract:
A three-dimensional image display apparatus includes a display panel configured to display an image and including gate lines, data lines, and pixels connected to the gate lines and the data lines, a data driver configured to drive the data lines, a gate driver configured to drive the gate lines, a lens panel configured to refract light of the image displayed by the display panel, a lens driver configured to drive the lens panel, a lens controller configured to control the lens driver, and a timing controller configured to control the data driver, the gate driver, and the lens driver in response to an image signal and a control signal. The lens controller and the timing controller are mounted on the same control board.
Abstract:
A display substrate for a display device includes: a substrate which includes a light blocking region defining a plurality of pixel areas disposed in a matrix, each pixel area having a length extending in a first direction, and a width extending in a second direction; a color filter overlapping a portion of the each pixel area of the plurality of pixel areas; and an alignment layer disposed on the color filter. The color filter includes a first edge parallel to the first direction and a second edge forming a predetermined angle with the first edge. The second edge is substantially parallel to an alignment direction of the alignment layer.
Abstract:
A gate driver includes stages each including a first-transistor including a gate-electrode receiving an output-signal of one previous-stage or a vertical-start-signal as a first input-signal, a first-electrode receiving the first input-signal, and a second-electrode connected to a first-node, a second-transistor including a gate-electrode connected to the first-node, a first-electrode receiving a first clock-signal, and a second-electrode connected to a first-output-terminal, a third-transistor including a gate-electrode receiving a second clock-signal, a first-electrode receiving a first power-voltage, and a second-electrode connected to the first-output-terminal, a fourth-transistor including a gate-electrode receiving a third clock-signal, a first-electrode receiving the third clock-signal, and a second-electrode connected to a second-node, a fifth-transistor including a gate-electrode connected to the second-node, a first-electrode receiving a second power-voltage, and a second-electrode connected to the first-node, and a sixth-transistor including a gate-electrode connected to the first-node, a first-electrode receiving the second power-voltage, and a second-electrode connected to the second-node.
Abstract:
A gate driver includes stages each including a first-transistor including a gate-electrode receiving an output-signal of one previous-stage or a vertical-start-signal as a first input-signal, a first-electrode receiving the first input-signal, and a second-electrode connected to a first-node, a second-transistor including a gate-electrode connected to the first-node, a first-electrode receiving a first clock-signal, and a second-electrode connected to a first-output-terminal, a third-transistor including a gate-electrode receiving a second clock-signal, a first-electrode receiving a first power-voltage, and a second-electrode connected to the first-output-terminal, a fourth-transistor including a gate-electrode receiving a third clock-signal, a first-electrode receiving the third clock-signal, and a second-electrode connected to a second-node, a fifth-transistor including a gate-electrode connected to the second-node, a first-electrode receiving a second power-voltage, and a second-electrode connected to the first-node, and a sixth-transistor including a gate-electrode connected to the first-node, a first-electrode receiving the second power-voltage, and a second-electrode connected to the second-node.
Abstract:
A transistor display panel including: a substrate; a gate electrode disposed on the substrate; a semiconductor that overlaps the gate electrode; an upper electrode disposed on the semiconductor; a source connection member and a drain connection member disposed on the same layer as the upper electrode and respectively connected with the semiconductor; a source electrode connected with the source connection member and the upper electrode; and a drain electrode connected with the drain connection member.