公开(公告)号：US20190227400A1

公开(公告)日：2019-07-25

申请号：US16251715

申请日：2019-01-18

Applicant: Samsung Display Co., Ltd.

Inventor： Hyunwook LEE ,  Pilgyu KANG ,  Xinxing LI ,  Solip JEONG

IPC: G02F1/1362 ,  G02F1/1339 ,  G02F1/1345 ,  G02F1/1343 ,  G02F1/1333 ,  G06T7/00

Abstract: A method of manufacturing a display device including the steps of: forming, on a first mother substrate, pixels including pixel electrodes, gate lines and data lines connected to the pixels; dividing the data lines into groups and connecting the data lines of the same group to one connection line; forming inspection electrodes on the first mother substrate overlapping a shot boundary portion of a mask, the inspection electrodes connected to a plurality of connection lines, respectively; preparing a second mother substrate; forming a common electrode on the second mother substrate; forming a mother panel including the first and second mother substrates and a liquid crystal layer therebetween; applying a first voltage to the common electrode and a second voltage to the inspection electrodes; and determining whether the inspection electrodes and the common electrode are short-circuited based on an image displayed in a display area of the mother panel.

公开(公告)号：US20190287475A1

公开(公告)日：2019-09-19

申请号：US16353994

申请日：2019-03-14

Applicant: Samsung Display Co., Ltd.

Inventor： Hyunwook LEE ,  Pilgyu KANG ,  Minchan LEE ,  Sungjin LEE ,  Chanyoung LIM ,  Solip JEONG

IPC: G09G3/36

Abstract: The present inventive concept is related to a display device in which a compensated voltage is applied to a gate line by compensating for a voltage drop of a voltage applied to the gate line.

公开(公告)号：US20160266457A1

公开(公告)日：2016-09-15

申请号：US15006259

申请日：2016-01-26

Applicant: Samsung Display Co., Ltd.

Inventor： Jun-hee LEE ,  Eoksu KIM ,  Wonjin KIM ,  Juyong PARK ,  Jungchul WOO ,  Hyunwook LEE

IPC: G02F1/1362 ,  G02F1/1368 ,  G02F1/1341 ,  G02F1/1343 ,  G02F1/1337 ,  H01L27/12 ,  G02F1/1335

CPC classification number: H01L27/124 ,  G02F1/1309 ,  G02F1/133351 ,  G02F1/1339 ,  G02F1/1341 ,  G02F2001/13415 ,  G02F2001/136254 ,  G02F2201/56 ,  G02F2203/69 ,  G09G3/006 ,  G09G2330/12 ,  H01L27/1218

Abstract: A liquid crystal cell panel includes a first substrate from which is formed a thin film transistor array substrate, the first substrate including a plurality of unit cells and test terminals which respectively correspond to the unit cells, and a second substrate which faces the first substrate and from which is formed a color filter substrate. The first substrate further includes a first cutting pattern at each of a plurality of corners thereof, and the second substrate includes a second cutting pattern at each of a plurality of corners thereof, the second cutting patterns corresponding one-to-one with the first cutting patterns. Corresponding first and second cutting patterns cross each other in a plan view, and the crossing first and second cutting patterns expose a test terminal adjacent to the crossing first and second cutting patterns to outside the liquid crystal cell panel.

Abstract translation: 液晶单元面板包括形成有薄膜晶体管阵列基板的第一基板，所述第一基板包括分别对应于所述单位单元的多个单元电池和测试端子，以及面向所述第一基板的第二基板和 由此形成滤色器基板。 第一基板还包括在其多个拐角中的每一个处的第一切割图案，并且第二基板在其多个拐角中的每一个处包括第二切割图案，第二切割图案与第一切割一一对应 模式。 对应的第一和第二切割图案在平面图中彼此交叉，并且交叉的第一和第二切割图案将与交叉的第一和第二切割图案相邻的测试端子暴露于液晶单元面板的外部。

公开(公告)号：US20220093029A1

公开(公告)日：2022-03-24

申请号：US17544862

申请日：2021-12-07

Applicant: Samsung Display Co., Ltd.

Inventor： Jaemin SEONG ,  Kangnam KIM ,  Jae-Hyun PARK ,  Hyunwook LEE

IPC: G09G3/20 ,  G09G3/3266 ,  G09G3/36 ,  G11C19/28

Abstract: A gate driver includes stages each including a first-transistor including a gate-electrode receiving an output-signal of one previous-stage or a vertical-start-signal as a first input-signal, a first-electrode receiving the first input-signal, and a second-electrode connected to a first-node, a second-transistor including a gate-electrode connected to the first-node, a first-electrode receiving a first clock-signal, and a second-electrode connected to a first-output-terminal, a third-transistor including a gate-electrode receiving a second clock-signal, a first-electrode receiving a first power-voltage, and a second-electrode connected to the first-output-terminal, a fourth-transistor including a gate-electrode receiving a third clock-signal, a first-electrode receiving the third clock-signal, and a second-electrode connected to a second-node, a fifth-transistor including a gate-electrode connected to the second-node, a first-electrode receiving a second power-voltage, and a second-electrode connected to the first-node, and a sixth-transistor including a gate-electrode connected to the first-node, a first-electrode receiving the second power-voltage, and a second-electrode connected to the second-node.

公开(公告)号：US20190266934A1

公开(公告)日：2019-08-29

申请号：US16268995

申请日：2019-02-06

Applicant: Samsung Display Co., Ltd.

Inventor： Jaemin SEONG ,  Kangnam KIM ,  Jae-Hyun PARK ,  Hyunwook LEE

IPC: G09G3/20

Abstract: A gate driver includes stages each including a first-transistor including a gate-electrode receiving an output-signal of one previous-stage or a vertical-start-signal as a first input-signal, a first-electrode receiving the first input-signal, and a second-electrode connected to a first-node, a second-transistor including a gate-electrode connected to the first-node, a first-electrode receiving a first clock-signal, and a second-electrode connected to a first-output-terminal, a third-transistor including a gate-electrode receiving a second clock-signal, a first-electrode receiving a first power-voltage, and a second-electrode connected to the first-output-terminal, a fourth-transistor including a gate-electrode receiving a third clock-signal, a first-electrode receiving the third clock-signal, and a second-electrode connected to a second-node, a fifth-transistor including a gate-electrode connected to the second-node, a first-electrode receiving a second power-voltage, and a second-electrode connected to the first-node, and a sixth-transistor including a gate-electrode connected to the first-node, a first-electrode receiving the second power-voltage, and a second-electrode connected to the second-node.