知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

11 条记录 (耗时 0.019 秒)

    All digital phase locked loop
    1.
    发明授权
    All digital phase locked loop 有权

    公开(公告)号：US10038451B2

    公开(公告)日：2018-07-31

    申请号：US15795703

    申请日：2017-10-27

    申请人： SK hynix Inc. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

    发明人： Jae Yoon Sim ,  Min Seob Lee ,  In Hwa Jung ,  Yong Ju Kim

    IPC分类号： H03L7/099 ,  H03L7/07

    CPC分类号： H03L7/0992 ,  H03L7/07 ,  H03L7/081 ,  H03L7/085 ,  H03L2207/50

    摘要： An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.

    Synapse array, pulse shaper circuit and neuromorphic system
    4.
    发明授权
    Synapse array, pulse shaper circuit and neuromorphic system 有权
    突触阵列，脉冲整形电路和神经形态系统

    公开(公告)号：US09418333B2

    公开(公告)日：2016-08-16

    申请号：US14165392

    申请日：2014-01-27

    申请人： SAMSUNG ELECTRONICS CO., LTD. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

    发明人： Jun Seok Kim ,  Jae Yoon Sim ,  Hyun Surk Ryu ,  Hwasuk Cho

    IPC分类号： G06F15/18 ,  G06N3/08 ,  G06N3/063 ,  G06N3/04 ,  G11C11/412

    CPC分类号： G06N3/063 ,  G06N3/049 ,  G11C11/412

    摘要： A synapse array based on a static random access memory (SRAM), a pulse shaper circuit, and a neuromorphic system are provided. The synapse array includes a plurality of synapse circuits. At least one synapse circuit among the plurality of synapse circuits includes at least one bias transistor and at least two cut-off transistors, and the at least one synapse circuit is configured to charge a membrane node of a neuron circuit connected with the at least one synapse circuit using a sub-threshold leakage current that passed through the at least one bias transistor.

    摘要翻译： 提供了基于静态随机存取存储器（SRAM），脉冲整形器电路和神经形态系统的突触阵列。 突触阵列包括多个突触电路。 所述多个突触电路中的至少一个突触电路包括至少一个偏置晶体管和至少两个截止晶体管，并且所述至少一个突触电路被配置为对与所述至少一个连接的神经元电路的膜节点进行充电 使用通过所述至少一个偏置晶体管的子阈值漏电流的突触电路。

    Low-power bandgap reference voltage generator using leakage current
    5.
    发明授权
    Low-power bandgap reference voltage generator using leakage current 有权

    公开(公告)号：US09671811B2

    公开(公告)日：2017-06-06

    申请号：US15150564

    申请日：2016-05-10

    申请人： POSTECH ACADEMY-INDUSTRY FOUNDATION

    发明人： Jae Yoon Sim ,  Jong Mi Lee ,  Young Woo Ji

    IPC分类号： G05F3/08

    CPC分类号： G05F3/08

    摘要： A low-power bandgap reference voltage generator using a leakage current may include: a medium voltage generation unit configured to generate a medium voltage based on the absolute temperature, using a leakage current; a low power amplifier configured to amplify the medium voltage and outputting an operational amplification voltage; and a reference voltage output unit configured to output a reference voltage based on the operational amplification voltage at a target level.

    Phase locked loop using direct digital frequency synthesizer
    6.
    发明授权
    Phase locked loop using direct digital frequency synthesizer 有权

    公开(公告)号：US10739811B2

    公开(公告)日：2020-08-11

    申请号：US16474524

    申请日：2017-11-30

    申请人： POSTECH ACADEMY-INDUSTRY FOUNDATION

    发明人： Jae Yoon Sim ,  Hwa Suk Cho

    IPC分类号： H03L7/10 ,  G06F1/03 ,  H03L7/081 ,  H03L7/083 ,  H03L7/197

    摘要： The present invention relates to a design technology of a phase locked loop (PLL) for generating an accurate clock frequency in a clock synchronization system.The present invention suggests a new structure based on a hardware description language (HDL), and thus reduces a chip area of a frequency synthesizer while obtaining a wide frequency operation range.Furthermore, since only the HDL is used, the entire frequency synthesizer becomes all-synthesizable, and auto layout (auto P&R) can be achieved through a tool, which makes it possible to reduce a design cost of a designer.

    SAR-type analog-digital converter using residue integration
    9.
    发明授权
    SAR-type analog-digital converter using residue integration 有权

    公开(公告)号：US10250277B1

    公开(公告)日：2019-04-02

    申请号：US15993432

    申请日：2018-05-30

    申请人： POSTECH ACADEMY-INDUSTRY FOUNDATION

    发明人： Jae Yoon Sim ,  Seungnam Choi

    IPC分类号： H03M1/14 ,  H03M1/16 ,  H03M1/38 ,  H03M3/00

    摘要： The present invention relates to a successive approximation register (SAR)-type analog-digital converter (ADC), which can amplify a residual voltage without a non-linearity problem caused by an output voltage of a residual voltage amplifier, thereby performing high-resolution analog-digital conversion at low power consumption.The SAR-type ADC may include: a coarse/fine SAR conversion unit configured to receive an analog input voltage and convert the received voltage into an MSB digital signal in a coarse SAR conversion mode, and receive a feedback voltage and convert the received voltage into an LSB digital signal in a fine SAR conversion mode; and a residue integration unit configured to repeatedly amplify a residual voltage with a predetermined gain by a predetermined number of times and output the amplified voltage as a final target multiple, the residual voltage corresponding to a voltage difference between the analog input voltage and an analog voltage obtained by converting the digital signal into an analog signal.