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    All digital phase locked loop
    1.
    发明授权
    All digital phase locked loop 有权

    公开(公告)号：US10038451B2

    公开(公告)日：2018-07-31

    申请号：US15795703

    申请日：2017-10-27

    申请人： SK hynix Inc. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

    发明人： Jae Yoon Sim ,  Min Seob Lee ,  In Hwa Jung ,  Yong Ju Kim

    IPC分类号： H03L7/099 ,  H03L7/07

    CPC分类号： H03L7/0992 ,  H03L7/07 ,  H03L7/081 ,  H03L7/085 ,  H03L2207/50

    摘要： An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.

    Test apparatus
    3.
    发明授权
    Test apparatus 有权

    公开(公告)号：US10983164B2

    公开(公告)日：2021-04-20

    申请号：US16733035

    申请日：2020-01-02

    申请人： SK hynix Inc. ,  KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION

    发明人： Chul Woo Kim ,  Dong Yoon Kim ,  In Hwa Jung ,  Yong Ju Kim

    IPC分类号： G01R31/319 ,  G06F11/22 ,  G01R31/28 ,  G01R31/3167

    摘要： A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers, and provides the second timing information corresponding to the timing differences to the transceivers.

    Test apparatus
    5.
    发明授权
    Test apparatus 有权

    公开(公告)号：US10557888B2

    公开(公告)日：2020-02-11

    申请号：US15650403

    申请日：2017-07-14

    申请人： SK hynix Inc. ,  KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION

    发明人： Chul Woo Kim ,  Dong Yoon Kim ,  In Hwa Jung ,  Yong Ju Kim

    IPC分类号： G01R31/319 ,  G06F11/22 ,  G01R31/28 ,  G01R31/3167

    摘要： A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers, and provides the second timing information corresponding to the timing differences to the transceivers.