-
公开(公告)号:US11469747B1
公开(公告)日:2022-10-11
申请号:US17551653
申请日:2021-12-15
申请人: SK hynix Inc.
发明人: Geun Ho Choi , Young Hyun Baek
摘要: A shift register generates a synthesized pulse having a different pulse width according to which one of a first phase pulse and a second phase pulse is inputted, generates an internal shifted synthesized pulse and a shifted synthesized pulse from the synthesized pulse, and generates a detection signal by detecting a pulse width of the internal shifted synthesized pulse. The shift register outputs the shifted synthesized pulse as one of a first shifted phase pulse and a second shifted phase pulse based on the detection signal.
-
公开(公告)号:US10074444B2
公开(公告)日:2018-09-11
申请号:US15048226
申请日:2016-02-19
申请人: SK hynix Inc.
发明人: Young Hyun Baek
CPC分类号: G11C29/44 , G11C29/78 , G11C29/783 , G11C29/789 , G11C29/812
摘要: A repair circuit may be provided. The repair circuit may include a latch array including a plurality of latch sets. The repair circuit may include a fuse array including a plurality of fuse sets, and configured to be written, in each fuse set, with repair address data and latch address data which defines a position of a latch set where the repair address data is to be stored, among the plurality of latch sets. The repair circuit may include a first decoder configured to cause data written in any one fuse set among the plurality of fuse sets to be outputted, and a second decoder configured to cause the repair address data to be stored in the latch set corresponding to the latch address data among the plurality of latch sets.
-
公开(公告)号:US10013305B2
公开(公告)日:2018-07-03
申请号:US15477228
申请日:2017-04-03
申请人: SK hynix Inc.
发明人: Soo Bin Lim , Young Hyun Baek
CPC分类号: G06F11/0793 , G06F11/0727 , G06F11/0751 , G06F11/079 , G11C17/16 , G11C29/36 , G11C29/38 , G11C29/40 , G11C29/44 , G11C29/4401 , G11C29/787 , G11C2029/4402
摘要: A semiconductor device and or method of repairing the semiconductor device may be provided. The semiconductor device may include an error information storage circuit. The error information storage circuit may be configured to latch an address to generate a latched fail address and a rupture control signal.
-
公开(公告)号:US09589669B1
公开(公告)日:2017-03-07
申请号:US15193588
申请日:2016-06-27
申请人: SK hynix Inc.
发明人: Young Hyun Baek , Bo Yeun Kim , Sang Hee Kim , Ji Eun Jang
CPC分类号: G11C29/027 , G11C7/20 , G11C8/14 , G11C17/16 , G11C17/18 , G11C29/46 , G11C29/76 , G11C29/78 , G11C2029/0407
摘要: A semiconductor system and semiconductor device may be provided. The semiconductor system may include a first semiconductor device configured to generate a test mode signal and configured to receive output data. The semiconductor system may include a second semiconductor device configured to enter a test mode, based on the test mode signal, and block the output data of data that is stored in redundancy memory cells connected to unrepaired redundancy word lines which are not used among redundancy word lines provided for replacing failed word lines.
摘要翻译: 可以提供半导体系统和半导体器件。 半导体系统可以包括被配置为生成测试模式信号并被配置为接收输出数据的第一半导体器件。 半导体系统可以包括被配置为基于测试模式信号进入测试模式的第二半导体器件,并且阻止存储在冗余存储器单元中的数据的输出数据,所述冗余存储单元连接到在冗余字中未使用的未修复冗余字线 提供用于替换失败字线的线。
-
-
-