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公开(公告)号:US09990978B2
公开(公告)日:2018-06-05
申请号:US15248361
申请日:2016-08-26
申请人: SK hynix Inc.
发明人: Bo Yeun Kim
IPC分类号: G11C7/10 , G11C11/406 , G11C11/408
CPC分类号: G11C11/40618 , G11C7/02 , G11C11/40622 , G11C11/4082 , G11C11/4087
摘要: A semiconductor device may be provided. The semiconductor device may include an address input circuit and a target address generation circuit. The address input circuit may be configured to latch a bank address and an address to generate a bank active signal and a latch address based on the execution of an active operation. The target address generation circuit may be configured to generate the latch address as a target address.
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公开(公告)号:US09589669B1
公开(公告)日:2017-03-07
申请号:US15193588
申请日:2016-06-27
申请人: SK hynix Inc.
发明人: Young Hyun Baek , Bo Yeun Kim , Sang Hee Kim , Ji Eun Jang
CPC分类号: G11C29/027 , G11C7/20 , G11C8/14 , G11C17/16 , G11C17/18 , G11C29/46 , G11C29/76 , G11C29/78 , G11C2029/0407
摘要: A semiconductor system and semiconductor device may be provided. The semiconductor system may include a first semiconductor device configured to generate a test mode signal and configured to receive output data. The semiconductor system may include a second semiconductor device configured to enter a test mode, based on the test mode signal, and block the output data of data that is stored in redundancy memory cells connected to unrepaired redundancy word lines which are not used among redundancy word lines provided for replacing failed word lines.
摘要翻译: 可以提供半导体系统和半导体器件。 半导体系统可以包括被配置为生成测试模式信号并被配置为接收输出数据的第一半导体器件。 半导体系统可以包括被配置为基于测试模式信号进入测试模式的第二半导体器件,并且阻止存储在冗余存储器单元中的数据的输出数据,所述冗余存储单元连接到在冗余字中未使用的未修复冗余字线 提供用于替换失败字线的线。
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公开(公告)号:US10297308B2
公开(公告)日:2019-05-21
申请号:US15971856
申请日:2018-05-04
申请人: SK hynix Inc.
发明人: Bo Yeun Kim
IPC分类号: G11C11/406 , G11C11/408 , G11C7/02
摘要: A semiconductor device may be provided. The semiconductor device may include an address input circuit and a target address generation circuit. The address input circuit may be configured to latch a bank address and an address to generate a bank active signal and a latch address based on the execution of an active operation. The target address generation circuit may be configured to generate the latch address as a target address.
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