公开(公告)号：US09275705B2

公开(公告)日：2016-03-01

申请号：US14858677

申请日：2015-09-18

Applicant: SK hynix Inc.

Inventor： Kyung-Hoon Kim

IPC: G11C5/14 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/106 ,  G11C7/1072 ,  G11C11/4091 ,  G11C16/0466 ,  G11C16/26

Abstract: An integrated circuit includes a variable resistance unit including at least one transistor that receives a control signal and changes a resistance through the transistor in response to the control signal in a programming operation mode and an information detection unit configured to detect programming information in response to an output voltage of the variable resistance unit in a normal operation mode.

公开(公告)号：US09793901B2

公开(公告)日：2017-10-17

申请号：US14994291

申请日：2016-01-13

Applicant: SK hynix Inc.

Inventor： Han-Kyu Chi ,  Kyung-Hoon Kim ,  Myeong-Jae Park ,  Taek-Sang Song ,  Tae-Wook Kang

IPC: H04L7/00 ,  H03L7/08 ,  H03K5/135 ,  H03L7/10 ,  H04L7/033 ,  H03K5/00

CPC classification number: H03L7/0807 ,  G11C7/222 ,  G11C11/4076 ,  H03K5/135 ,  H03K2005/00019 ,  H03L7/081 ,  H03L7/0812 ,  H03L7/105 ,  H03L2207/06 ,  H04L7/0037 ,  H04L7/0331

Abstract: An integrated circuit may include: a phase detector suitable for generating a delay control signal by comparing the phases of first and second clock signals to first and second target positions, a variable delay unit suitable for shifting the first and second clock signals to the first and second target positions, respectively, in response to the delay control signal, and a position controller suitable for varying the first and second target positions according to an operation mode.

公开(公告)号：US09787296B1

公开(公告)日：2017-10-10

申请号：US15234954

申请日：2016-08-11

Applicant: SK hynix Inc.

Inventor： Sung-Eun Lee ,  Kyung-Hoon Kim ,  Myeong-Jae Park ,  Woo-Yeol Shin ,  Han-Kyu Chi ,  Yong-Ju Kim

IPC: H03K5/159 ,  H03K21/38 ,  H03K5/00

CPC classification number: H03K5/159 ,  H03K5/131 ,  H03K21/38 ,  H03K2005/00078 ,  H03K2005/00247 ,  H03K2005/00273

Abstract: A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.

公开(公告)号：US09887831B2

公开(公告)日：2018-02-06

申请号：US15206046

申请日：2016-07-08

Applicant: SK hynix Inc.

Inventor： Woo-Yeol Shin ,  Myeong-Jae Park ,  Kyu-Young Kim ,  Han-Kyu Chi ,  Sung-Eun Lee ,  Kyung-Hoon Kim

IPC: H03D3/24 ,  H04L7/033 ,  H03L7/081 ,  H04L7/00

CPC classification number: H04L7/0331 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/0814 ,  H04L7/0025 ,  H04L7/0337

Abstract: A clock data recovery circuit may include: a phase comparison unit suitable for comparing input data with a phase of a multi-phase clock, and for generating an up/down signal corresponding to the comparison result; a filtering unit suitable for counting the up/down signal based on an upper threshold value and a lower threshold value, for setting, when an overflow occurs, the lower threshold value to an initial value for the count of the up/down signal, or when a underflow occurs, the upper threshold value to the initial value for the count of the up/down signal, and for generating a control code corresponding to one of the underflow and the overflow; and a phase rotating unit suitable for adjusting the phase of the multi-phase clock in response to the control code outputted from the filtering unit.