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6 条记录 (耗时 0.02 秒)

    BUFFER CIRCUIT
    1.
    发明申请
    BUFFER CIRCUIT 有权

    公开(公告)号：US20220069813A1

    公开(公告)日：2022-03-03

    申请号：US17171719

    申请日：2021-02-09

    申请人： SK hynix Inc.

    发明人： Sun Ki Cho ,  Dong Uc Ko ,  Yang Ho Sur ,  Jun Yong Song ,  Sung Gil Jang ,  Hae Kang Jung ,  Min Sung Cheon ,  Chang Kyu Choi ,  Tae Jin Hwang

    IPC分类号： H03K5/02 ,  H03F3/45

    摘要： A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.

    Controller and memory system for refreshing memory based on fail bits and temperature
    4.
    发明授权
    Controller and memory system for refreshing memory based on fail bits and temperature 有权

    公开(公告)号：US11742015B2

    公开(公告)日：2023-08-29

    申请号：US17340922

    申请日：2021-06-07

    申请人： SK hynix Inc.

    发明人： Hyun Ju Yoon ,  Min Kang ,  Dong Uc Ko ,  Dong Keun Kim ,  Young Su Oh ,  Jun Hyun Chun

    IPC分类号： G11C11/406

    CPC分类号： G11C11/40626 ,  G11C11/40615

    摘要： A memory system is provided to include a storage device including memory cells for storing data, and a controller in communication with an external device and configured to control the storage device based on a request from the external device. The controller is configured to receive a request from the external device to perform a refresh operation of re-writing stored data in the memory cells, read data from the memory cells included in the storage device, set a refresh period based on a number of fail bits included in the read data and a temperature of the controller or the storage device, and perform the refresh operation of the storage device based on the refresh period.

    Volatile memory device, storage device, and operating method of decreasing a leakage current
    5.
    发明授权
    Volatile memory device, storage device, and operating method of decreasing a leakage current 有权

    公开(公告)号：US11587608B2

    公开(公告)日：2023-02-21

    申请号：US17337231

    申请日：2021-06-02

    申请人： SK hynix Inc.

    发明人： Hyun Ju Yoon ,  Min Kang ,  Dong Uc Ko ,  Dong Keun Kim ,  Young Su Oh ,  Jun Hyun Chun

    IPC分类号： G11C8/10 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4076 ,  G11C11/4091

    摘要： There are provided a volatile memory device, and an operating method. The volatile memory device includes: a plurality of memory cells arranged in rows and columns and structured to store data; word lines; bit lines; a row decoder; a column decoder; and a control logic coupled to communicate with the row and column decoders and configured to, in an active period, provide the row decoder with a first command, and provide the column decoder with a second command, wherein the row decoder is further configured to: apply a first word line voltage higher than a ground voltage to a selected word line, from when the first command is provided; and for a duration over which the row decoder is activated, apply either a second word line voltage lower than the first word line voltage to the selected word line or no voltage to the selected word line.