公开(公告)号：US10074441B2

公开(公告)日：2018-09-11

申请号：US15174748

申请日：2016-06-06

申请人： SK hynix Inc.

发明人： Byoung-Sung You ,  Jae-Hyoung Ko

IPC分类号： G11C16/34 ,  G06F12/02 ,  G11C16/10 ,  G11C16/28 ,  G11C16/30 ,  G11C16/04

CPC分类号： G11C16/349 ,  G06F12/0253 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/30 ,  G11C16/3445 ,  G11C16/3459

摘要： A memory device includes a pass/fail check circuit configured to compare the number of memory cells, which are verified as being a program fail based on a result of verifying program operations of a first group of memory cells of a plurality of memory cells, with a first reference bit number, and to check whether the first group of memory cells is a pass or fail and a control circuit configured to control the pass/fail check circuit to recheck whether the first group of memory cells is the pass or fail based on a second reference bit number smaller than the first reference bit number when the first group of memory cells is found to be the pass based on a result of a pass/fail check operation of the pass/fail check circuit.

公开(公告)号：US09984001B2

公开(公告)日：2018-05-29

申请号：US15204401

申请日：2016-07-07

申请人： SK hynix Inc.

发明人： Byoung-Sung You ,  Jin-Woong Kim ,  Jong-Min Lee

IPC分类号： G11C16/04 ,  G06F12/0868 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0804

CPC分类号： G06F12/0868 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0804 ,  G06F2212/1021 ,  G06F2212/2022 ,  G06F2212/281 ,  G06F2212/312 ,  G06F2212/608 ,  G06F2212/7203

摘要： A memory system may include a plurality of first and second memory devices each comprising M-bit multi-level cells (MLCs), M-bit multi-buffers, and transmission buffers, a cache memory suitable for caching data inputted to or outputted from the plurality of first and second memory devices, and a controller suitable for programming program data cached by the cache memory to a memory device selected among the first and second memory devices by transferring the program data to M-bit multi-buffers of the selected memory device whenever the program data are cached by M bits into the cache memory, and controlling the selected memory device to perform a necessary preparation operation, except for a secondary preparation operation, of a program preparation operation, until an input of the program data is ended or the M-bit multi-buffers of the selected memory device are full.

公开(公告)号：US10073623B2

公开(公告)日：2018-09-11

申请号：US15636756

申请日：2017-06-29

申请人： SK hynix Inc.

发明人： Byoung-Sung You

IPC分类号： G11C5/06 ,  G06F3/06 ,  G06F13/16 ,  G06F13/18

CPC分类号： G06F3/0604 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/0246 ,  G06F13/1668 ,  G06F13/18 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/7205 ,  G06F2212/7208

摘要： A memory system, may include: a memory device including a plurality of memory blocks each including a plurality of stacked word lines; and a controller suitable for dividing the plurality of word lines into two or more word line groups according to heights thereof, programming data of a relatively high access frequency into a word line group having word lines of relatively low physical heights and data of a relatively low access frequency into a word line group having word lines of relatively high physical heights among the word line groups included in each of the memory blocks.

公开(公告)号：US09851899B2

公开(公告)日：2017-12-26

申请号：US15498153

申请日：2017-04-26

申请人： SK hynix Inc.

发明人： Byoung-Sung You

IPC分类号： G11C11/56 ,  G06F3/06 ,  G11C16/04 ,  G11C16/34

CPC分类号： G06F3/06 ,  G06F3/061 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/107 ,  G11C16/3454

摘要： A nonvolatile memory device includes a multi-level cell which stores M-bit data at a time and M number of latches for respectively storing M-bit data on a single bit basis. A controller sequentially latches M-bit data of the multi-level cell into the M number of latches, respectively, during a first half read period, and sequentially outputs the latched M-bit data in the M number of latches during a second half read period.

公开(公告)号：US11068335B2

公开(公告)日：2021-07-20

申请号：US14743729

申请日：2015-06-18

申请人： SK hynix Inc.

发明人： Byoung-Sung You

IPC分类号： G06F11/10 ,  G06F12/0873 ,  G06F12/14

摘要： A memory system may include a first memory device including a first input/output buffer, a second memory device including a second input/output buffer, and a cache memory suitable for selectively and temporarily storing first and second data to be respectively programmed in the first and second memory devices. The first data is programmed to the first memory device in a first program section by being stored in the cache memory only in a first monopoly section of the first program section. The second data is programmed to the second memory device in a second program section by being stored in the cache memory only in a second monopoly section of a second program section. The first monopoly section and the second monopoly section are set not to overlap each other.

公开(公告)号：US10719266B2

公开(公告)日：2020-07-21

申请号：US15893858

申请日：2018-02-12

申请人： SK hynix Inc.

发明人： Byeong-Gyu Park ,  Hyunjun Kim ,  Byoung-Sung You

IPC分类号： G06F11/10 ,  G06F12/06 ,  G06F13/42 ,  G06F3/06 ,  G11C29/04 ,  G11C29/52

摘要： A controller includes: a processor suitable for controlling a memory device to read map data stored in a memory and read out a physical address corresponding to data requested by a host to be read; a counter suitable for obtaining reliability information on the map data stored in the memory; a determining unit suitable for activating a pre-pumping mode when reliability of the map data is poor; a deciding unit suitable for determining a first target die of a pre-pumping operation for reading the data in the activated pre-pumping mode; and a pumping unit suitable for controlling the memory device to perform the pre-pumping operation on the first target die during a background operation for reading out the physical address.

公开(公告)号：US09666270B2

公开(公告)日：2017-05-30

申请号：US14960117

申请日：2015-12-04

申请人： SK hynix Inc.

发明人： Byoung-Sung You

IPC分类号： G11C11/56 ,  G06F3/06 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

CPC分类号： G06F3/06 ,  G06F3/061 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/107 ,  G11C16/3454

摘要： A nonvolatile memory device includes a multi-level cell which stores M-bit data at a time and M number of latches for respectively storing M-bit data on a single bit basis. A controller sequentially latches M-bit data of the multi-level cell into the M number of latches, respectively, during a first half read period, and sequentially outputs the latched M-bit data in the M number of latches during a second half read period.