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    METHODS OF FABRICATING EMBEDDED ELECTRONIC DEVICES INCLUDING CHARGE TRAP MEMORY CELLS
    3.
    发明申请
    METHODS OF FABRICATING EMBEDDED ELECTRONIC DEVICES INCLUDING CHARGE TRAP MEMORY CELLS 有权
    嵌入式电子设备的方法，包括充电陷阱存储器单元

    公开(公告)号：US20160358931A1

    公开(公告)日：2016-12-08

    申请号：US14885371

    申请日：2015-10-16

    Applicant: SK hynix Inc.

    Inventor： Tae Ho LEE ,  Young Joon KWON ,  Sung Kun PARK

    IPC: H01L27/115 ,  H01L21/02 ,  H01L29/51 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/311

    CPC classification number: H01L29/518 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66833

    Abstract: A method of fabricating an embedded electronic device including charge trap memory cells that includes forming a tunnel insulation layer, a charge trap layer and a sacrificial insulation layer on a substrate having a first region and a second region. The tunnel insulation layer, the charge trap layer and the sacrificial insulation layer which are stacked on the second region of the substrate are selectively removed. A well region is formed in an upper region of the second region of the substrate. The sacrificial insulation layer remaining over the first region is removed to expose the charge trap layer remaining over the first region. A blocking insulation layer and a gate insulation layer are formed on the exposed charge trap layer over the first region and on the second region of the substrate, respectively.

    Abstract translation: 一种制造包括电荷陷阱存储单元的嵌入式电子器件的方法，包括在具有第一区域和第二区域的衬底上形成隧道绝缘层，电荷陷阱层和牺牲绝缘层。 选择性地去除层叠在基板的第二区域上的隧道绝缘层，电荷陷阱层和牺牲绝缘层。 阱区域形成在衬底的第二区域的上部区域中。 残留在第一区域上的牺牲绝缘层被去除以暴露残留在第一区域上的电荷陷阱层。 分别在基板的第一区域和第二区域上的暴露的电荷陷阱层上形成隔离绝缘层和栅极绝缘层。

    MEMORY DEVICE, MEMORY SYSTEM INCLUDING MEMORY DEVICE, AND METHOD OF OPERATING MEMORY SYSTEM
    4.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM INCLUDING MEMORY DEVICE, AND METHOD OF OPERATING MEMORY SYSTEM 有权

    公开(公告)号：US20210182144A1

    公开(公告)日：2021-06-17

    申请号：US16856866

    申请日：2020-04-23

    Applicant: SK hynix Inc.

    Inventor： Tae Ho LEE ,  Byung Ryul KIM ,  Dae Il CHOI ,  Yong Hwan HONG

    IPC: G06F11/10 ,  G06F12/02 ,  G06F12/0882 ,  G06F9/30

    Abstract: The present technology relates to a memory device, a memory system including the same, and a method of operating the memory system. The memory device includes a cam block including a plurality of pages, peripheral circuits configured to read a cam data of a page unit that is stored in a selected page among the plurality of pages of the cam block during a cam data read operation, a cam data read controller configured to receive the read cam data of the page unit from the peripheral circuits during a cam data load operation and configured to output the received cam data of the page unit as output cam data, and a control logic configured to control the peripheral circuits to perform the cam data read operation and the cam data load operation. The cam data read controller stops the cam data load operation based on a check data that is included in the read cam data of the page unit.

    NONVOLATILE MEMORY DEVICES HAVING SINGLE-LAYERED FLOATING GATES
    5.
    发明申请
    NONVOLATILE MEMORY DEVICES HAVING SINGLE-LAYERED FLOATING GATES 有权
    具有单层浮动门的非易失性存储器件

    公开(公告)号：US20150270360A1

    公开(公告)日：2015-09-24

    申请号：US14470652

    申请日：2014-08-27

    Applicant: SK hynix Inc.

    Inventor： Tae Ho LEE

    IPC: H01L29/417 ,  H01L27/115 ,  H01L29/788

    CPC classification number: H01L29/41758 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/788 ,  H01L29/7887

    Abstract: A nonvolatile memory device includes a plurality of twin cells arrayed on a substrate. Each of the plurality of twin cells includes a drain mesa protruding from a surface of a substrate. A first source and a second source are disposed in the substrate and spaced apart from the drain mesa. A first floating gate overlaps with a first sidewall surface of the drain mesa and extends onto the first source, and a second floating gate overlaps with a second sidewall surface of the drain mesa and extends onto the second source. Related methods are also provided.

    Abstract translation: 非易失性存储器件包括排列在衬底上的多个双电池。 多个双孔单元中的每一个包括从基板的表面突出的排水台面。 第一源极和第二源极设置在衬底中并与漏极台面间隔开。 第一浮栅与漏极台面的第一侧壁表面重叠并且延伸到第一源极上，并且第二浮栅与漏极台面的第二侧壁表面重叠并且延伸到第二源极上。 还提供了相关方法。

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