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公开(公告)号：US11289403B2
公开(公告)日：2022-03-29
申请号：US16728051
申请日：2019-12-27
发明人： Misaki Komatsu , Katsuya Fukase
IPC分类号： H01L23/48 , H01L21/02 , H01L23/522 , H01L23/528 , H05K1/02 , H01L23/498 , H01L21/48
摘要： A multi-layer substrate includes: a first insulating layer; a conductor layer that is provided on an upper surface of the first insulating layer and that has a penetrating portion; a second insulating layer that covers the conductor layer and that is stacked on the upper surface of the first insulating layer; a via hole that penetrates the second insulating layer from an upper surface of the second insulating layer to reach an inside of the first insulating layer and that includes the penetrating portion; and an insulating member with which the via hole is filled. The conductor layer has a portion exposed in the via hole, and the insulating member covers an upper surface and a lower surface of the conductor layer exposed in the via hole through the penetrating portion of the conductor layer.
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公开(公告)号：US09253897B2
公开(公告)日：2016-02-02
申请号：US14329073
申请日：2014-07-11
CPC分类号： H05K3/4007 , H05K3/465 , H05K2203/0392 , H05K2203/1461 , H05K2203/1563
摘要： A wiring substrate includes an insulating layer, a first pad, and a solder resist layer. The first pad is embedded in the insulating layer. The solder resist layer is provided on an upper surface of the insulating layer. The solder resist layer is formed with an opening portion through which the recess portion is exposed. An adjacent portion of the solder resist layer adjacent to a peripheral portion of the opening portion covers a peripheral portion of the upper surface of the first pad and protrudes from the peripheral portion of the upper surface of the first pad toward the center portion of the first pad so as to cover above the recess portion. Surfaces of the first pad being in contact with the insulating layer are smaller in roughness than the upper surface of the insulating layer and the peripheral portion of the upper surface of the first pad.
摘要翻译： 布线基板包括绝缘层，第一焊盘和阻焊层。 第一焊盘嵌入绝缘层。 阻焊层设置在绝缘层的上表面上。 阻焊层形成有凹部露出的开口部。 与阻挡层的与开口部的周边部相邻的相邻部分覆盖第一焊盘的上表面的周边部分，并且从第一焊盘的上表面的周边部朝向第一焊盘的中心部分突出 垫以覆盖凹部的上方。 与绝缘层接触的第一焊盘的表面的粗糙度小于绝缘层的上表面和第一焊盘的上表面的周边部分。
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公开(公告)号：US20150014020A1
公开(公告)日：2015-01-15
申请号：US14329073
申请日：2014-07-11
IPC分类号： H05K1/11
CPC分类号： H05K3/4007 , H05K3/465 , H05K2203/0392 , H05K2203/1461 , H05K2203/1563
摘要： A wiring substrate includes an insulating layer, a first pad, and a solder resist layer. The first pad is embedded in the insulating layer. The solder resist layer is provided on an upper surface of the insulating layer. The solder resist layer is formed with an opening portion through which the recess portion is exposed. An adjacent portion of the solder resist layer adjacent to a peripheral portion of the opening portion covers a peripheral portion of the upper surface of the first pad and protrudes from the peripheral portion of the upper surface of the first pad toward the center portion of the first pad so as to cover above the recess portion. Surfaces of the first pad being in contact with the insulating layer are smaller in roughness than the upper surface of the insulating layer and the peripheral portion of the upper surface of the first pad.
摘要翻译： 布线基板包括绝缘层，第一焊盘和阻焊层。 第一焊盘嵌入绝缘层。 阻焊层设置在绝缘层的上表面上。 阻焊层形成有凹部露出的开口部。 与阻挡层的与开口部的周边部相邻的相邻部分覆盖第一焊盘的上表面的周边部分，并且从第一焊盘的上表面的周边部朝向第一焊盘的中心部分突出 垫以覆盖凹部的上方。 与绝缘层接触的第一焊盘的表面的粗糙度小于绝缘层的上表面和第一焊盘的上表面的周边部分。
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公开(公告)号：US10892217B2
公开(公告)日：2021-01-12
申请号：US16523573
申请日：2019-07-26
发明人： Takashi Arai , Fumimasa Katagiri , Katsuya Fukase
IPC分类号： H01L23/528 , H01L23/498 , H01L21/48
摘要： A wiring substrate includes first wiring portions, an insulation layer covering the first wiring portions, openings extending through the insulation layer in a thickness-wise direction, partially exposing upper surfaces of the first wiring portions, and differing from each other in capacity, and second wiring portions, each of which includes a via wiring filling one of the openings and a columnar connection terminal electrically connected to the via wiring and arranged on an upper surface of the insulation layer. The via wiring includes an electrolytic plated layer and an electroless plating structure including N layers (N is integer and ≥0) arranged between the electrolytic plated layer and the upper surface of the first wiring portion exposed in a bottom of the opening. The via wiring is formed so that the electroless plating structure has a thickness that increases as a capacity of the opening filled with the via wiring is increased.
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公开(公告)号：US10321574B2
公开(公告)日：2019-06-11
申请号：US15718280
申请日：2017-09-28
发明人： Junji Sato , Katsuya Fukase
IPC分类号： H05K1/18 , H01L21/48 , H01L23/31 , H01L23/498 , H01L23/00 , H05K1/11 , H05K3/00 , H05K3/30 , H05K3/46
摘要： An electronic component-embedded substrate includes a core substrate, a cavity penetrating the core substrate, a wiring layer formed on one surface of the core substrate, a support pattern extending over the cavity and configured to divide the cavity into a plurality of component embedding areas, an insulation wall portion arranged on a part of the support pattern in the cavity and formed of the same material as the core substrate, a plurality of electronic components each of which is mounted in each of the plurality of component embedding areas, and an insulating material filling an inside of the cavity.
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公开(公告)号：US10080293B2
公开(公告)日：2018-09-18
申请号：US15658532
申请日：2017-07-25
发明人： Junji Sato , Katsuya Fukase
IPC分类号： H05K1/16 , H05K1/18 , H01L23/13 , H01L23/498 , H01L21/683 , H01L21/48 , H01L23/00
CPC分类号： H05K1/186 , H01L21/4857 , H01L21/486 , H01L21/6836 , H01L23/13 , H01L23/145 , H01L23/15 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/73 , H01L2221/68345 , H01L2221/68359 , H01L2224/13101 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/15311 , H01L2924/19041 , H01L2924/19102 , H05K1/181 , H05K3/4644 , H05K2201/10015 , H05K2201/10515 , H05K2201/10522 , H01L2924/014 , H01L2924/00014 , H01L2924/00012
摘要： An electronic component-embedded board includes: a core substrate; a cavity which penetrates the core substrate; a wiring layer formed on one face of the core substrate; a component mounting pattern formed of the same material as the wiring layer and laid across the cavity to partition the cavity into through holes in plan view; an electronic component mounted on the component mounting pattern and arranged inside the cavity; a first insulating layer formed on the one face of the core substrate to cover one face of the electronic component; and a second insulating layer formed on the other face of the core substrate to cover the other face of the electronic component. The cavity is filled with the first insulating layer and the second insulating layer.
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公开(公告)号：US09966331B2
公开(公告)日：2018-05-08
申请号：US15056515
申请日：2016-02-29
IPC分类号： H01L23/498 , H01L25/10
CPC分类号： H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L25/105 , H01L2224/73204 , H01L2924/15311
摘要： The wiring substrate includes an insulation layer that includes a lower surface, an upper surface, and an intermediate surface located between the lower surface and the upper surface. A first wiring layer is formed on the lower surface of the insulation layer. A second wiring layer is formed on the intermediate surface of the insulation layer. A recess is formed in the upper surface of the insulation layer. The recess overlaps, in a plan view, a first through hole that extends through the insulation layer. The first through hole is filled with a via wiring, which is formed integrally with the first wiring layer. A bump is formed integrally with the via wiring and projected into the recess. An upper end surface of the bump is located above an upper surface of the second wiring layer.
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公开(公告)号：US10340214B2
公开(公告)日：2019-07-02
申请号：US15714307
申请日：2017-09-25
发明人： Junji Sato , Hitoshi Kondo , Katsuya Fukase
IPC分类号： H01L23/498 , H05K3/34 , H01L21/48 , H01L21/683 , H01L23/31 , H01L23/00 , H01L21/56 , H01L21/66
摘要： A carrier base material-added wiring substrate includes a wiring substrate and a carrier base material. The wiring substrate includes an insulation layer, a wiring layer arranged on a lower surface of the insulation layer, and a solder resist layer that covers the lower surface of the insulation layer and includes an opening that exposes a portion of the wiring layer as an external connection terminal. The carrier base material is adhered by an adhesive layer to the solder resist layer. The carrier base material includes an opening that is in communication with the opening of the solder resist layer and exposes the external connection terminal. The opening of the carrier base material has a diameter that is smaller than that of the opening of the solder resist layer.
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公开(公告)号：US09433109B2
公开(公告)日：2016-08-30
申请号：US14308853
申请日：2014-06-19
发明人： Kentaro Kaneko , Katsuya Fukase
CPC分类号： H05K3/4682 , H01L2224/16237 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2224/83385 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19106 , H05K1/112 , H05K1/113 , H05K1/181 , H05K3/3436 , H05K3/381 , H05K3/4007 , H05K2201/0367 , H05K2201/09045 , H05K2201/09481 , H05K2201/096 , H05K2201/09827 , H05K2201/10674 , H05K2201/10977 , H05K2201/2072 , H05K2203/0152 , H05K2203/0376 , H05K2203/1184 , H05K2203/308
摘要： A wiring substrate includes an insulating layer that is an outermost layer of the wiring substrate and includes an external exposed surface, a pad forming part formed on a side of the external exposed surface, and a pad that projects from the external exposed surface. The pad forming part includes a recess part recessed from the external exposed surface, and a weir part that projects from the external exposed surface and encompasses the recess part from a plan view. The pad includes a pad body formed within the recess part and the weir part, and an eave part formed on the weir part. The pad body includes an end part that projects to the weir part. The eave part projects in a horizontal direction from the end part of the pad body. The end part of the pad body includes a flat surface.
摘要翻译： 布线基板包括绝缘层，其是布线基板的最外层，并且包括外部暴露表面，形成在外部暴露表面侧的焊盘形成部分以及从外部暴露表面突出的焊盘。 衬垫形成部分包括从外部暴露表面凹陷的凹陷部分和从外部暴露表面突出并从俯视图包围凹部的堰部分。 衬垫包括形成在凹部和堰部内的垫体，以及形成在堰部上的檐部。 垫体包括突出到堰部分的端部。 檐部从垫体的端部沿水平方向突出。 垫体的端部包括平坦表面。
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公开(公告)号：US09313904B2
公开(公告)日：2016-04-12
申请号：US14310076
申请日：2014-06-20
发明人： Kentaro Kaneko , Katsuya Fukase
CPC分类号： H05K3/465 , H01L2224/16225 , H01L2224/73204 , H01L2924/15311 , H05K3/4679 , H05K2201/09527 , H05K2203/025
摘要： A wiring board includes a first wiring layer including a first conductive layer and a second conductive layer coating a first surface and a side surface of the first conductive layer. A first insulating layer covers a first surface and a side surface of the second conductive layer so as to expose a second surface of the first conductive layer opposite to the first surface of the first conductive layer. A second wiring layer is stacked on a first surface of the first insulating layer and is electrically connected to the first wiring layer. The first surface and the side surface of the first conductive layer are smooth surfaces while the first surface and the side surface of the second conductive layer are roughened-surfaces.
摘要翻译： 布线基板包括第一布线层，第一布线层包括第一导电层和涂覆第一导电层的第一表面和侧表面的第二导电层。 第一绝缘层覆盖第二导电层的第一表面和侧表面，以暴露与第一导电层的第一表面相对的第一导电层的第二表面。 第二布线层堆叠在第一绝缘层的第一表面上并与第一布线层电连接。 第一导电层的第一表面和侧表面是平滑表面，而第二导电层的第一表面和侧表面是粗糙表面。
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