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公开(公告)号：US11721679B2
公开(公告)日：2023-08-08
申请号：US17396308
申请日：2021-08-06
发明人： Yanggyoo Jung , Chulwoo Kim , Hyo-Chang Ryu , Yun Seok Choi
IPC分类号： H01L25/16 , H01L23/528 , H01L23/48 , H01L23/367 , H01L23/00 , H01L21/78 , H01L23/498 , H01L21/683 , H01L21/48 , H01L25/00 , H01L23/538
CPC分类号： H01L25/16 , H01L21/486 , H01L21/4853 , H01L21/6835 , H01L21/78 , H01L23/3675 , H01L23/481 , H01L23/49816 , H01L23/528 , H01L23/5386 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/97 , H01L25/50 , H01L2221/68372 , H01L2224/16145 , H01L2224/16146 , H01L2224/1703 , H01L2224/17181 , H01L2224/81005 , H01L2224/95001
摘要： A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.
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公开(公告)号：US11670565B2
公开(公告)日：2023-06-06
申请号：US17307181
申请日：2021-05-04
发明人： Hyo-Chang Ryu , Chulwoo Kim , Juhyun Lyu , Sanghyun Lee , Yun Seok Choi
IPC分类号： H01L23/367 , H01L25/065 , H01L23/00 , H01L25/00
CPC分类号： H01L23/3675 , H01L24/32 , H01L25/0655 , H01L23/367 , H01L25/50 , H01L2224/32237 , H01L2924/3511
摘要： A semiconductor package includes a first substrate, a first chip structure and a second chip structure spaced apart from each other on the first substrate, a gap region being defined between the first and second chip structures, and a heat dissipation member covering the first chip structure, the second chip structure, and the first substrate, the heat dissipation member including a first trench in an inner top surface of the heat dissipation member, wherein the first trench vertically overlaps with the gap region and has a width greater than a width of the gap region, and wherein the first trench vertically overlaps with at least a portion of a top surface of the first chip structure or a portion of a top surface of the second chip structure.
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公开(公告)号：US11418737B2
公开(公告)日：2022-08-16
申请号：US17404198
申请日：2021-08-17
发明人： Dong Pan Lim , Irina Kim , Young Il Seo , Jeong Guk Lee , Yun Seok Choi , Eun Doo Heo
摘要： An image processing device including a memory; and at least one image signal processor configured to: generate, using a first neural network, a feature value indicating whether to correct a global pixel value sensed during a unit frame interval, and generate a feature signal including the feature value; generate an image signal by merging the global pixel value with the feature signal; split a pixel value included in the image signal into a first sub-pixel value and a second sub-pixel value, split a frame feature signal included in the image signal into a first sub-feature value corresponding to the first sub-pixel value and a second sub-feature value corresponding to the second sub-pixel value, and generate a first sub-image signal including the first sub-pixel value and the first sub-feature value, and a second sub-image signal including the second sub-pixel value and the second sub-feature value; and sequentially correct the first sub-image signal and the second sub-image signal using a second neural network.
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公开(公告)号：US10734367B2
公开(公告)日：2020-08-04
申请号：US16232159
申请日：2018-12-26
发明人： Seung-Kwan Ryu , Yonghwan Kwon , Yun Seok Choi , Chajea Jo , Taeje Cho
摘要： A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.
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公开(公告)号：US11887919B2
公开(公告)日：2024-01-30
申请号：US17181116
申请日：2021-02-22
发明人： Yun Seok Choi
IPC分类号： H01L23/498 , H01L25/065 , H01L25/18 , H01L21/48 , H01L23/367 , H01L23/14 , H01L23/00
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/4853 , H01L23/49811 , H01L23/49894 , H01L25/0655 , H01L25/18 , H01L23/147 , H01L23/3675 , H01L24/73 , H01L2224/73204
摘要： A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a semiconductor chip on the first surface of the upper substrate, a buffer layer on the second surface of the upper substrate, a mold layer between the second surface of the upper substrate and the buffer layer, a plurality of through-electrodes penetrating the upper substrate and the mold layer, an interconnection layer between the first surface of the upper substrate and the semiconductor chip and configured to electrically connect the semiconductor chip to the plurality of through-electrodes, and a plurality of bumps disposed on the buffer layer, spaced apart from the mold layer, and electrically connected to the plurality of through-electrodes. The mold layer includes an insulating material of which a coefficient of thermal expansion is greater than that of the upper substrate.
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公开(公告)号：US20230335476A1
公开(公告)日：2023-10-19
申请号：US18164851
申请日：2023-02-06
发明人： Dae Hun Lee , Sung Bum Kim , Yun Seok Choi
CPC分类号： H01L23/49816 , H01L21/4853 , H01L21/565 , H01L24/16 , H01L24/32 , H01L24/73 , H01L23/49833 , H01L23/49838 , H01L23/49866 , H01L23/3128 , H01L23/3135 , H01L25/105 , H01L2924/1438 , H01L2924/1436 , H01L2924/1431 , H01L2924/3512 , H01L21/563 , H01L2224/73204 , H01L2224/32225 , H01L2224/16227 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058
摘要： A semiconductor package includes a wiring structure including a first insulating layer and a first wiring pad. The first wiring pad is in the first insulating layer. The package includes a semiconductor chip on the wiring structure, and an interposer on the semiconductor chip. The interposer includes a second insulating layer and a second wiring pad, and the second wiring pad is in the second insulating layer. The package includes a first connecting structure including a first metal layer and a second metal layer surrounding the first metal layer. The first metal layer includes a lower metal layer adjacent to the wiring structure and an upper metal layer adjacent to the interposer, and the first connecting structure connects the first wiring pad and the second wiring pad. The package includes a mold layer between the wiring structure and the interposer.
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公开(公告)号：US11515290B2
公开(公告)日：2022-11-29
申请号：US17021112
申请日：2020-09-15
发明人： Yun Seok Choi
IPC分类号： H01L25/065 , H01L23/538 , H01L23/367 , H01L23/31 , H01L23/48
摘要： A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a lower semiconductor chip disposed on the first surface of the upper substrate, a plurality of conductive pillars disposed on the first surface of the upper substrate at at least one side of the lower semiconductor chip, and an upper semiconductor chip disposed on the second surface of the upper substrate. The lower semiconductor chip and the plurality of conductive pillars are connected to the first surface of the upper substrate, and the upper semiconductor chip is connected to the second surface of the upper substrate.
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公开(公告)号：US11217503B2
公开(公告)日：2022-01-04
申请号：US16748061
申请日：2020-01-21
发明人： Yang Gyoo Jung , Chul Woo Kim , Hyo-Chang Ryu , Seung-Kwan Ryu , Yun Seok Choi
IPC分类号： H01L23/367 , H01L23/42 , H01L25/10 , H01L25/065 , H01L23/498 , H05K1/18 , H01L23/00
摘要： A semiconductor package includes a substrate and an interposer disposed on the substrate. The interposer comprises a first surface facing the substrate and a second surface facing away from the substrate. A first logic semiconductor chip is disposed on the first surface of the interposer and is spaced apart from the substrate in a first direction orthogonal to an upper surface of the substrate. A first memory package is disposed on the second surface of the interposer. A second memory package is disposed on the second surface of the interposer and is spaced apart from the first memory package in a second direction that is parallel to the upper surface of the substrate. A first heat transfer unit is disposed on a surface of the substrate facing the first logic semiconductor chip. The first heat transfer unit is spaced apart from the first logic semiconductor chip in the first direction.
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公开(公告)号：US09892915B2
公开(公告)日：2018-02-13
申请号：US15285570
申请日：2016-10-05
发明人： Seung Yun Yang , Seung Hyun Lee , Kyoung Sil Park , Yool Kang , Yi Seul Kim , Yun Seok Choi
IPC分类号： H01L21/311 , H01L21/027 , H01L21/02 , H01L21/308
CPC分类号： H01L21/0271 , B82Y10/00 , B82Y30/00 , H01L21/02115 , H01L21/02282 , H01L21/02359 , H01L21/3081 , H01L51/0048
摘要： A manufacturing method of a semiconductor device includes forming a hard mask layer on a semiconductor substrate using a hard mask composition. Hard mask patterns are formed by patterning the hard mask layer. Semiconductor patterns are formed by etching the semiconductor substrate using the hard mask patterns. The hard mask composition includes a plurality of first carbon nanotubes (CNTs) having a first length, a plurality of second CNTs having a second length, which is at least 3 times the first length, and a dispersing agent in which the first CNTs and the second CNTs are dispersed. The total mass of the first CNTs is 1 to 2.5 times the total mass of the second CNTs.
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公开(公告)号：US12002784B2
公开(公告)日：2024-06-04
申请号：US17983018
申请日：2022-11-08
发明人： Yun Seok Choi
IPC分类号： H01L25/065 , H01L23/31 , H01L23/367 , H01L23/48 , H01L23/538
CPC分类号： H01L25/0652 , H01L23/3128 , H01L23/3135 , H01L23/367 , H01L23/481 , H01L23/5383 , H01L23/5385
摘要： A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a lower semiconductor chip disposed on the first surface of the upper substrate, a plurality of conductive pillars disposed on the first surface of the upper substrate at at least one side of the lower semiconductor chip, and an upper semiconductor chip disposed on the second surface of the upper substrate. The lower semiconductor chip and the plurality of conductive pillars are connected to the first surface of the upper substrate, and the upper semiconductor chip is connected to the second surface of the upper substrate.
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