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    INTEGRATED CIRCUIT FOR PERFORMING LINK EQUALIZATION
    1.
    发明申请
    INTEGRATED CIRCUIT FOR PERFORMING LINK EQUALIZATION 有权

    公开(公告)号：US20240388477A1

    公开(公告)日：2024-11-21

    申请号：US18626953

    申请日：2024-04-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyu-Min Park ,  Byung Jik Kim ,  Seung-Woo Lim ,  Walter Jun

    IPC: H04L25/03 ,  H04B10/077

    Abstract: A method for operating an integrated circuit, including: completing a first link equalization operation with an external integrated circuit; receiving a first signal transmitted by an external transmitter included in the external integrated circuit during an operation at an internal receiver included in the integrated circuit; measuring an eye margin of the first signal at the internal receiver; comparing the measured eye phase with a threshold eye margin to obtain and store a comparison result; transmitting the comparison result as a second signal to an external receiver included in the external integrated circuit using an internal transmitter included in the internal integrated circuit; and performing a second link equalization operation between the external transmitter and the external receiver based on the second signal.

    Storage devices including a plurality of planes and methods of operating the storage devices
    5.
    发明授权
    Storage devices including a plurality of planes and methods of operating the storage devices 有权

    公开(公告)号：US11182301B2

    公开(公告)日：2021-11-23

    申请号：US16546598

    申请日：2019-08-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin-oh Ahn ,  Hyun-wook Shin ,  Walter Jun

    IPC: G06F12/0882 ,  G06F3/06 ,  G06F12/02 ,  G11C11/56

    Abstract: In a method of operating a storage device including a non-volatile memory (NVM), the non-volatile memory including a memory cell array, the memory cell array including a first plane and a second plane, the method includes receiving a read command set for data sensing of the first and second plane; simultaneously loading first page data stored in the first plane into a first page buffer of the first plane and second page data stored in the second plane into a second page buffer of the second plane based on the read command set; receiving a data output command set that includes the first plane; and continuously transmitting the first page data and the second page databased on the data output command set.

    Data storage device using host memory buffer and method of operating the same
    6.
    发明授权
    Data storage device using host memory buffer and method of operating the same 有权

    公开(公告)号：US10983722B2

    公开(公告)日：2021-04-20

    申请号：US16506613

    申请日：2019-07-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-Seok Kim ,  Walter Jun

    IPC: G06F12/00 ,  G06F3/06 ,  G06F1/3206 ,  H04L9/08 ,  H04L9/32 ,  G06F9/30

    Abstract: A data storage device includes a nonvolatile memory device, a storage controller and a mapping controller. The nonvolatile memory device stores an execution code that controls operations of the data storage device. The storage controller uploads and stores the execution code from the nonvolatile memory device to a host memory buffer included in an external host device, and downloads the execution code in realtime from the host memory buffer to execute the execution code that is downloaded from the host memory buffer. The mapping controller manages a mapping table including mapping relations between the execution code and host addresses of the host memory buffer at which the execution code is stored. A speed of accessing the execution code is increased and performance of the data storage device is enhanced by using the host memory buffer as storage of the execution code to control the operation of the data storage device.

    MEMORY DEVICE AND RECLAIMING METHOD OF THE MEMORY DEVICE
    7.
    发明申请
    MEMORY DEVICE AND RECLAIMING METHOD OF THE MEMORY DEVICE 审中-公开

    公开(公告)号：US20190146688A1

    公开(公告)日：2019-05-16

    申请号：US16120832

    申请日：2018-09-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hee-Tai OH ,  Walter Jun

    IPC: G06F3/06

    Abstract: A memory device includes a nonvolatile memory having a first block and a memory controller configured to exchange data with the nonvolatile memory. The memory controller includes a first processor to divide the first block into first and second domains, a second processor to generate a reclaim signal by determining whether to perform reclaiming on each of the first and second domains and a third processor performer which reclaims each of the first and second domains according to the reclaim signal and merges the first and second domains.

    RAID storage device, host, and RAID system
    8.
    发明授权
    RAID storage device, host, and RAID system 有权

    公开(公告)号：US11625193B2

    公开(公告)日：2023-04-11

    申请号：US17351506

    申请日：2021-06-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jae Hwan Lim ,  Seung-Woo Lim ,  Sung-Wook Kim ,  So-Geum Kim ,  Jae Eun Kim ,  Dae Hun You ,  Walter Jun

    IPC: G06F3/06

    Abstract: A redundant array of independent disks (RAID) storage device including; a memory device including first memory devices configured to store at least one of data chunks and corresponding parity (data chunks/parity) and a second memory device configured to serve as a spare memory region, and a RAID controller including a RAID internal memory configured to store a count table and configured to control performing of a rebuild operation in response to a command received from a host, wherein upon identification of a failed first memory device, the RAID controller accesses used regions of non-failed first memory devices based on the count table and rebuilds data of the failed first memory device using the second memory device.

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