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公开(公告)号:US11829626B2
公开(公告)日:2023-11-28
申请号:US17360099
申请日:2021-06-28
发明人: Jaehwan Lim , Sung-Wook Kim , Jae Eun Kim , Daehun You , Walter Jun
IPC分类号: G06F3/06 , G06F1/324 , G06F11/07 , G06F11/30 , G11C16/32 , G11C16/34 , G06F1/3225 , G06F1/3237 , G11C7/04 , G11C7/22
CPC分类号: G06F3/0647 , G06F1/324 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G06F11/0772 , G06F11/3058
摘要: A storage device includes a nonvolatile memory device and a controller that accesses the nonvolatile memory device based on a request of an external host device, receives a first clock signal from the external host device, generates a second clock signal through frequency multiplication of the first clock signal, and communicates with the external host device based on the second clock signal. The controller requests the external host device to adjust a multiplication ratio for the frequency multiplication of the first clock signal.
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公开(公告)号:US11740966B2
公开(公告)日:2023-08-29
申请号:US17539898
申请日:2021-12-01
发明人: Young San Kang , Walter Jun , Ye Jin Cho , Sung Tack Hong
CPC分类号: G06F11/1068 , G06F11/076 , G06F11/0772 , G06F13/1668 , H03M13/1108
摘要: A memory device, and an operating method of the memory device and a host device are provided. The method of operating a memory device includes receiving a command for requesting an Eye Open Monitor (EOM) operation performance from a host device, receiving pattern data including data and non-data from the host device, performing the EOM operation which performs an error count to correspond to the data, and does not perform the error count on the non-data, and transmitting an EOM response signal including the error count result to the host device.
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公开(公告)号:US11699469B2
公开(公告)日:2023-07-11
申请号:US17400368
申请日:2021-08-12
发明人: Young San Kang , Jeong Hur , Walter Jun , Kwang Won Park , Kyoung Back Lee
CPC分类号: G11C7/1096 , G11C7/1045 , G11C7/1057 , G11C7/1069 , G11C7/1084
摘要: Provided are an operating method of a host device, an operating method of a memory device, and a memory system. The operating method of a host device includes transmitting a request command for performing an eye-opening monitor (EOM) operation to a memory device, transmitting a parameter for performing the EOM operation to the memory device, transmitting pattern data for performing the EOM operation to the memory device, and receiving a first response signal including a result of the EOM operation performed based on the parameter and the pattern data from the memory device.
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公开(公告)号:US11182301B2
公开(公告)日:2021-11-23
申请号:US16546598
申请日:2019-08-21
发明人: Jin-oh Ahn , Hyun-wook Shin , Walter Jun
IPC分类号: G06F12/0882 , G06F3/06 , G06F12/02 , G11C11/56
摘要: In a method of operating a storage device including a non-volatile memory (NVM), the non-volatile memory including a memory cell array, the memory cell array including a first plane and a second plane, the method includes receiving a read command set for data sensing of the first and second plane; simultaneously loading first page data stored in the first plane into a first page buffer of the first plane and second page data stored in the second plane into a second page buffer of the second plane based on the read command set; receiving a data output command set that includes the first plane; and continuously transmitting the first page data and the second page databased on the data output command set.
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公开(公告)号:US10983722B2
公开(公告)日:2021-04-20
申请号:US16506613
申请日:2019-07-09
发明人: Hyun-Seok Kim , Walter Jun
摘要: A data storage device includes a nonvolatile memory device, a storage controller and a mapping controller. The nonvolatile memory device stores an execution code that controls operations of the data storage device. The storage controller uploads and stores the execution code from the nonvolatile memory device to a host memory buffer included in an external host device, and downloads the execution code in realtime from the host memory buffer to execute the execution code that is downloaded from the host memory buffer. The mapping controller manages a mapping table including mapping relations between the execution code and host addresses of the host memory buffer at which the execution code is stored. A speed of accessing the execution code is increased and performance of the data storage device is enhanced by using the host memory buffer as storage of the execution code to control the operation of the data storage device.
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公开(公告)号:US20190146688A1
公开(公告)日:2019-05-16
申请号:US16120832
申请日:2018-09-04
发明人: Hee-Tai OH , Walter Jun
IPC分类号: G06F3/06
摘要: A memory device includes a nonvolatile memory having a first block and a memory controller configured to exchange data with the nonvolatile memory. The memory controller includes a first processor to divide the first block into first and second domains, a second processor to generate a reclaim signal by determining whether to perform reclaiming on each of the first and second domains and a third processor performer which reclaims each of the first and second domains according to the reclaim signal and merges the first and second domains.
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公开(公告)号:US11625193B2
公开(公告)日:2023-04-11
申请号:US17351506
申请日:2021-06-18
发明人: Jae Hwan Lim , Seung-Woo Lim , Sung-Wook Kim , So-Geum Kim , Jae Eun Kim , Dae Hun You , Walter Jun
IPC分类号: G06F3/06
摘要: A redundant array of independent disks (RAID) storage device including; a memory device including first memory devices configured to store at least one of data chunks and corresponding parity (data chunks/parity) and a second memory device configured to serve as a spare memory region, and a RAID controller including a RAID internal memory configured to store a count table and configured to control performing of a rebuild operation in response to a command received from a host, wherein upon identification of a failed first memory device, the RAID controller accesses used regions of non-failed first memory devices based on the count table and rebuilds data of the failed first memory device using the second memory device.
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公开(公告)号:US20220137848A1
公开(公告)日:2022-05-05
申请号:US17360099
申请日:2021-06-28
发明人: Jaehwan Lim , Sung-Wook Kim , Jae Eun Kim , Daehun You , Walter Jun
摘要: A storage device includes a nonvolatile memory device and a controller that accesses the nonvolatile memory device based on a request of an external host device, receives a first clock signal from the external host device, generates a second clock signal through frequency multiplication of the first clock signal, and communicates with the external host device based on the second clock signal. The controller requests the external host device to adjust a multiplication ratio for the frequency multiplication of the first clock signal.
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公开(公告)号:US11281549B2
公开(公告)日:2022-03-22
申请号:US16507170
申请日:2019-07-10
发明人: Yeon Woo Kim , Jea Young Kwon , Walter Jun
摘要: A storage device includes an integrity checking module checking integrity of data stored in a first host memory buffer (HMB) address of an HMB in a host coupled to the storage device, and an HMB mapping module mapping, if the integrity checking module determines the data as corrupted, the first HMB address to a second address.
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公开(公告)号:US11733872B2
公开(公告)日:2023-08-22
申请号:US17706137
申请日:2022-03-28
发明人: Jaehwan Lim , Walter Jun , Jaeeun Kim , Jihoon Kim , Kihyeon Myung , Hyunjung Yoo , Jungwoo Lee
CPC分类号: G06F3/0613 , G06F3/0656 , G06F3/0673 , G06F13/4221 , G06F2213/0026
摘要: A system includes a transmission device and a reception device that are connected through a link. The reception device includes a reception buffer configured to receive and store transaction layer packets and a reception flow controller configured to generate flow control packets by monitoring an occupation state of the reception buffer. The transmission device includes a transmission buffer, a transmission flow controller and a dynamic frequency controller. The transmission buffer stores pending transaction layer packets to be transferred to the reception device. The transmission flow controller controls a flow of transaction layer packets to be transferred to the reception device based on the flow control packets received from the reception device. The dynamic frequency controller controls a frequency of an internal clock signal of the transmission device by monitoring a state of the transmission buffer and a state of the transmission flow controller.
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