公开(公告)号：US20250118672A1

公开(公告)日：2025-04-10

申请号：US18759447

申请日：2024-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Sub Song ,  Eunkyeong Park ,  Seokbeom Yong

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/14 ,  H01L23/498 ,  H01L23/522 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor packaging structure is provided including first through third routing layers. Each of the first through third routing layers includes a first through a third plurality of signal wires and a first through a third plurality of ground wires arranged alternately in a first horizontal direction. A plurality of vias connect the first to third ground wires to each other. The first to third signal wires and the first to third ground wires extend in a second horizontal direction intersecting the first horizontal direction. Each signal wire among the first to third signal wires is separated from any other signal wires. The first to third pluralities of signal wires overlap each other, and the first to third pluralities of ground wires overlap each other.

公开(公告)号：US20240047409A1

公开(公告)日：2024-02-08

申请号：US18188368

申请日：2023-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Sub Song ,  Seongho Yoon ,  Ki-Hong Jeong

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/528 ,  H01L23/495

CPC classification number: H01L24/73 ,  H01L25/16 ,  H01L23/5283 ,  H01L23/4952 ,  H01L24/85 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2224/73207

Abstract: A semiconductor package includes a package substrate having opposing first and second surfaces, a control chip on the first surface, a mode selection connection terminal between the control chip and the package substrate, a stack structure comprising stacked memory chips spaced apart from the control chip on the first surface, a first power pad and a wire pad that are spaced apart at the first surface, a first external connection terminal on the second surface, and first and second interconnection lines in the package substrate. The first power pad and the wire pad are spaced apart from the control chip. The first interconnection line connects the first power pad to the first external connection terminal. The second interconnection line connects the wire pad to the mode selection connection terminal. The first external connection terminal is configured to provide a ground voltage or a power voltage.

公开(公告)号：US11791321B2

公开(公告)日：2023-10-17

申请号：US17580047

申请日：2022-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Young Lee ,  Dongok Kwak ,  Boseong Kim ,  Sang Sub Song ,  Joonyoung Oh

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/3025

Abstract: A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.

公开(公告)号：US11848308B2

公开(公告)日：2023-12-19

申请号：US17325907

申请日：2021-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wansoo Park ,  Sang Sub Song ,  Kyung Suk Oh

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: Disclosed is a semiconductor package comprising a substrate, a chip stack including semiconductor chips stacked in an ascending stepwise shape on the substrate, first power/ground wires through which the substrate is connected to a lowermost semiconductor chip of the chip stack and neighboring semiconductor chips of the chip stack are connected to each other, and a second power/ground wire that extends from a first semiconductor chip and is connected to the substrate. The first semiconductor chip is one semiconductor chip other than the lowermost semiconductor chip and an uppermost semiconductor chip of the chip stack. The chip stack includes a first stack and a second stack on the first stack. The second stack constitutes a channel separate from that of the first stack.

公开(公告)号：US11452206B2

公开(公告)日：2022-09-20

申请号：US17029222

申请日：2020-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Jae Lee ,  Youngdong Kim ,  Sang Sub Song ,  Ki-Hong Jeong

IPC: H05K1/00 ,  H05K1/11 ,  H01R12/71

Abstract: A card-type solid state drive (SSD) including: a substrate that has a first surface and a second surface facing each other; a memory controller and a nonvolatile memory device that are on the first surface; a plurality of functional terminals on the second surface; and a plurality of thermal terminals on the second surface, wherein the functional terminals include first-row functional terminals, second-row functional terminals, and third-row functional terminals, wherein at least one of the first-row functional terminals, at least one of the second-row functional terminals, and at least one of the third-row functional terminals are electrically connected to the memory controller or the nonvolatile memory device, and wherein the thermal terminals are not electrically connected to the memory controller or the nonvolatile memory device.

公开(公告)号：US11330731B2

公开(公告)日：2022-05-10

申请号：US17036294

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Jae Lee ,  Sang Sub Song

IPC: H05K7/02 ,  H05K7/04 ,  H05K5/02 ,  G06K7/00

Abstract: An electric apparatus includes a substrate having a ground pattern on a top surface of the substrate; a conductive housing on the ground pattern and having an insertion space; a conductive connector disposed between the ground pattern and the conductive housing and connected to the ground pattern and the conductive housing, wherein the conductive housing is fixed to the substrate via the conductive connector; and a conductive cover coupled to the conductive housing, wherein the conductive cover is configured to move from a first position, at which the conductive cover externally opens the insertion space, to a second position, at which the conductive cover closes the insertion space.

公开(公告)号：US11251169B2

公开(公告)日：2022-02-15

申请号：US16549917

申请日：2019-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Young Lee ,  Dongok Kwak ,  Boseong Kim ,  Sang Sub Song ,  Joonyoung Oh

IPC: H01L23/31 ,  H01L25/10 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00

Abstract: A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.