公开(公告)号：US09947644B2

公开(公告)日：2018-04-17

申请号：US15268658

申请日：2016-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinhee Hong ,  Wansoo Park ,  Chul Park

IPC: H01L23/498 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2224/85399

Abstract: A semiconductor package is provided. The semiconductor package may include a plurality of memory chips, which are mounted on a top surface of a package substrate, and a plurality of controller chips, which are vertically stacked on at least one of top and bottom surfaces of the package substrate.

公开(公告)号：US11848308B2

公开(公告)日：2023-12-19

申请号：US17325907

申请日：2021-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wansoo Park ,  Sang Sub Song ,  Kyung Suk Oh

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: Disclosed is a semiconductor package comprising a substrate, a chip stack including semiconductor chips stacked in an ascending stepwise shape on the substrate, first power/ground wires through which the substrate is connected to a lowermost semiconductor chip of the chip stack and neighboring semiconductor chips of the chip stack are connected to each other, and a second power/ground wire that extends from a first semiconductor chip and is connected to the substrate. The first semiconductor chip is one semiconductor chip other than the lowermost semiconductor chip and an uppermost semiconductor chip of the chip stack. The chip stack includes a first stack and a second stack on the first stack. The second stack constitutes a channel separate from that of the first stack.

公开(公告)号：US20250118714A1

公开(公告)日：2025-04-10

申请号：US18647087

申请日：2024-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keumhee Ma ,  Wansoo Park

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip and directly bonded to the first semiconductor chip, a third semiconductor chip on the second semiconductor chip and directly bonded to the second semiconductor chip, and a molding layer on an upper surface of the first semiconductor chip and on a sidewall of the second semiconductor chip and a sidewall of the third semiconductor chip, wherein the third semiconductor chip includes a third semiconductor substrate including an upper surface at a level, which is lower than an upper surface of the molding layer, and a third upper insulation layer on the upper surface of the third semiconductor substrate, the upper surface of the molding layer, and an inner sidewall of the molding layer.

公开(公告)号：US12062647B2

公开(公告)日：2024-08-13

申请号：US17457660

申请日：2021-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeho Lee ,  Jinhyun Kim ,  Wansoo Park

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip disposed on the first redistribution substrate, a first mold layer that covers the first semiconductor chip and the first redistribution substrate, a second redistribution substrate disposed on the first mold layer, a second semiconductor chip disposed on the second redistribution substrate, where the second semiconductor chip includes a second-chip first conductive bump that does not overlap the first semiconductor chip, a first sidewall that overlaps the first semiconductor chip, and a second sidewall that does not overlap the first semiconductor chip, wherein the first sidewall and the second sidewall are opposite to each other, and a first mold via that penetrates the first mold layer connects the second-chip first conductive bump to the first redistribution substrate, and overlaps the second-chip first conductive bump.