公开(公告)号：US20240047409A1

公开(公告)日：2024-02-08

申请号：US18188368

申请日：2023-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Sub Song ,  Seongho Yoon ,  Ki-Hong Jeong

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/528 ,  H01L23/495

CPC classification number: H01L24/73 ,  H01L25/16 ,  H01L23/5283 ,  H01L23/4952 ,  H01L24/85 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2224/73207

Abstract: A semiconductor package includes a package substrate having opposing first and second surfaces, a control chip on the first surface, a mode selection connection terminal between the control chip and the package substrate, a stack structure comprising stacked memory chips spaced apart from the control chip on the first surface, a first power pad and a wire pad that are spaced apart at the first surface, a first external connection terminal on the second surface, and first and second interconnection lines in the package substrate. The first power pad and the wire pad are spaced apart from the control chip. The first interconnection line connects the first power pad to the first external connection terminal. The second interconnection line connects the wire pad to the mode selection connection terminal. The first external connection terminal is configured to provide a ground voltage or a power voltage.