公开(公告)号：US11871571B2

公开(公告)日：2024-01-09

申请号：US17517137

申请日：2021-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H01L23/498 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522

CPC classification number: H10B43/27 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L29/408 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US11387249B2

公开(公告)日：2022-07-12

申请号：US16708482

申请日：2019-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L27/11575 ,  H01L23/498 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522 ,  H01L27/11565

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US08980731B2

公开(公告)日：2015-03-17

申请号：US13724632

申请日：2012-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Ho Kim ,  Sunghae Lee ,  Hanvit Yang ,  Dongwoo Kim ,  Chaeho Kim ,  Daehyun Jang ,  Ju-Eun Kim ,  Yong-Hoon Son ,  Sangryol Yang ,  Myoungbum Lee ,  Kihyun Hwang

IPC: H01L21/04 ,  H01L21/82 ,  H01L21/336 ,  H01L21/3205 ,  H01L29/76 ,  H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L21/04 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.

Abstract translation: 提供了形成半导体器件的方法。 所述方法可以包括形成在衬底上交替和重复堆叠的第一和第二层，以及形成穿透第一层和第二层的开口。 所述方法还可以包括在开口中形成第一半导体图案。 所述方法还可以包括在第一半导体图案上形成绝缘图案。 所述方法还可以包括在绝缘图案上形成第二半导体图案。 所述方法还可以包括在第一半导体图案中提供掺杂剂。 此外，所述方法可以包括热处理第一半导体图案的一部分以形成第三半导体图案。

公开(公告)号：USRE50280E1

公开(公告)日：2025-01-21

申请号：US17840850

申请日：2022-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

公开(公告)号：US20220359566A1

公开(公告)日：2022-11-10

申请号：US17870037

申请日：2022-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L27/11575 ,  H01L23/498 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522 ,  H01L27/11565

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US09281361B2

公开(公告)日：2016-03-08

申请号：US14028912

申请日：2013-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwan Choi ,  Bo-Young Lee ,  Myoungbum Lee

IPC: H01L29/06 ,  H01L21/764 ,  H01L27/115

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L27/11529

Abstract: A semiconductor device includes a plurality of gate structures on a substrate, the plurality of gate structures including a gate metal pattern and delimiting air gaps formed therebetween, an insulating layer on the plurality of gate structures, and a porous insulating layer between the plurality of gate structures and the insulating layer, the porous insulating layer configured to cross the plurality of gate structures to delimit the air gaps.

Abstract translation: 半导体器件包括在衬底上的多个栅极结构，所述多个栅极结构包括栅极金属图案和形成在其间的限定气隙，多个栅极结构上的绝缘层和多个栅极之间的多孔绝缘层 结构和绝缘层，所述多孔绝缘层被配置成跨越所述多个栅极结构以限定所述气隙。

公开(公告)号：US09171860B2

公开(公告)日：2015-10-27

申请号：US14331582

申请日：2014-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee

IPC: H01L27/115

CPC classification number: H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, and a plurality of gate electrodes. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicular to the semiconductor substrate. The gate electrodes include a first gate electrode and a second gate electrode. The first gate electrode is disposed on the memory cell region to intersect the active pillars. The second gate electrode is disposed on the contact region, connected to the first gate electrode and comprising metal material.

Abstract translation: 三维非易失性存储器件及其制造方法包括半导体衬底，多个有源柱和多个栅电极。 半导体衬底包括存储单元区域和接触区域。 活性柱在垂直于半导体衬底的存储单元区域中延伸。 栅电极包括第一栅电极和第二栅电极。 第一栅电极设置在存储单元区域上以与有源支柱相交。 第二栅电极设置在接触区域上，连接到第一栅电极并且包括金属材料。

公开(公告)号：US20240155840A1

公开(公告)日：2024-05-09

申请号：US18416095

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H10B43/27 ,  H01L23/498 ,  H01L23/522 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50

CPC classification number: H10B43/27 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L29/408 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H01L2924/0002

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US20220037355A1

公开(公告)日：2022-02-03

申请号：US17497417

申请日：2021-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L27/11575 ,  H01L23/498 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522 ,  H01L27/11565

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US10546872B2

公开(公告)日：2020-01-28

申请号：US15634597

申请日：2017-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L27/11575 ,  H01L23/498 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522 ,  H01L27/11565

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.