公开(公告)号：US10553484B2

公开(公告)日：2020-02-04

申请号：US15959783

申请日：2018-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Chan Gwak ,  Hwi Chan Jun ,  Heon Jong Shin ,  So Ra You ,  Sang Hyun Lee ,  In Chan Hwang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a plurality of active regions spaced apart from each other and extending linearly in parallel on a substrate. A gate electrode crosses the plurality of active regions, and respective drain regions are on and/or in respective ones of the active regions on a first side of the gate electrode and respective source regions are on and/or in respective ones of the active regions on a second side of the gate electrode. A drain plug is disposed on the drain regions and a source plug is disposed on the source regions. A gate plug is disposed on the gate electrode between the drain plug and the source plug such that a straight line passing through a center of the drain plug and a center of the source plug intersects the gate plug.

公开(公告)号：US20250079265A1

公开(公告)日：2025-03-06

申请号：US18457311

申请日：2023-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Cheol NA ,  Kyoung Woo Le ,  Min Chan Gwak ,  Guk Hee Kim ,  Beom Jin Kim ,  Young Woo Kim ,  Anthony Dongick Lee ,  Myeong Gyoon Chae

IPC: H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a substrate that includes a first surface and a second surface, a first source/drain pattern disposed on the first surface of the substrate, a second source/drain pattern disposed on the first surface of the, a first source/drain contact disposed on the first source/drain pattern and connected to the first source/drain pattern, a second source/drain contact disposed on the second source/drain pattern and connected to the second source/drain pattern, a rear wiring line disposed on the second surface of the substrate, a first contact connection via that connects the rear wiring line with the first source/drain contact, a second contact connection via that connects the rear wiring line with the second source/drain contact and is spaced apart from the first contact connection via, and an air gap structure disposed between the first contact connection via and the second contact connection via.

公开(公告)号：US10340219B2

公开(公告)日：2019-07-02

申请号：US15868379

申请日：2018-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seul Ki Hong ,  Heon Jong Shin ,  Hwi Chan Jun ,  Min Chan Gwak

IPC: H01L29/66 ,  H01L21/321 ,  H01L23/485 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/78 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088

Abstract: A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction. A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.

公开(公告)号：US20240304513A1

公开(公告)日：2024-09-12

申请号：US18397389

申请日：2023-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anthony Dongick Lee ,  Min Chan Gwak ,  Guk Hee Kim ,  Young Woo Kim ,  Sang Cheol Na ,  Kyoung Woo Lee

IPC: H01L23/367 ,  H01L21/683 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L23/3672 ,  H01L21/6835 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L2221/68309

Abstract: A semiconductor device includes an active pattern on a first surface of a substrate and extending in a first direction, a field insulating film on the first surface and a side surface of the active pattern, a gate structure on the active pattern and field insulating film and extending in a second direction intersecting the first direction, a source/drain area on a side surface of the gate structure and contacting the active pattern, and a through-contact extending in a third direction perpendicular to the first and second directions and extending through the field insulating film. The device further includes a buried pattern in the substrate contacting the through-contact, a backside wiring structure on a second surface of the substrate and electrically connected to the buried pattern, and a heat-dissipating structure in the substrate adjacent to the buried pattern. The heat-dissipating structure fills a trench extending from the second surface into the substrate.

公开(公告)号：US10818549B2

公开(公告)日：2020-10-27

申请号：US16724483

申请日：2019-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Chan Gwak ,  Hwi Chan Jun ,  Heon Jong Shin ,  So Ra You ,  Sang Hyun Lee ,  In Chan Hwang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L29/775

Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.

公开(公告)号：US10658288B2

公开(公告)日：2020-05-19

申请号：US16420825

申请日：2019-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seul Ki Hong ,  Heon Jong Shin ,  Hwi Chan Jun ,  Min Chan Gwak

IPC: H01L23/522 ,  H01L29/78 ,  H01L27/088 ,  H01L23/532 ,  H01L23/535 ,  H01L29/06 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/321 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L21/768 ,  H01L23/485 ,  H01L27/12 ,  H01L21/84

Abstract: A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction. A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.

公开(公告)号：US20240282829A1

公开(公告)日：2024-08-22

申请号：US18500797

申请日：2023-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Woo Kim ,  Kyoung Woo Lee ,  Min Chan Gwak ,  Guk Hee Kim ,  Sang Cheol Na ,  Anthony Dongick Lee

IPC: H01L29/417 ,  H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate that has first and second surfaces opposite to each other in a first direction, a first fin-type pattern that protrudes in the first direction from the first surface of the substrate and extends in a second direction, a first source/drain pattern on the first fin-type pattern, a first source/drain contact on the first source/drain pattern, a contact connection via that extends in the first direction and is electrically connected to the first source/drain contact, a buried conductive pattern that is in the substrate, is electrically connected to the contact connection via, and has first and second surfaces opposite to each other in the first direction, the first surface of the buried conductive pattern facing the first source/drain contact, and first buried insulating liners that extend along sidewalls and along the first surface of the buried conductive pattern.

公开(公告)号：US11778801B2

公开(公告)日：2023-10-03

申请号：US17185102

申请日：2021-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Hun Jung ,  Heon Jong Shin ,  Min Chan Gwak ,  Sung Moon Lee ,  Jeong Ki Hwang

IPC: H10B10/00 ,  H01L23/528 ,  H01L21/768

CPC classification number: H10B10/12 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/528 ,  H10B10/125

Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.

公开(公告)号：US11721581B2

公开(公告)日：2023-08-08

申请号：US17031279

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Chan Gwak ,  Hwi Chan Jun ,  Heon Jong Shin ,  So Ra You ,  Sang Hyun Lee ,  In Chan Hwang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L29/775

CPC classification number: H01L21/76897 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/456 ,  H01L29/775 ,  H01L29/785

Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.

公开(公告)号：US20190131171A1

公开(公告)日：2019-05-02

申请号：US15959783

申请日：2018-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Chan Gwak ,  HWI CHAN JUN ,  HEON JONG SHIN ,  SO RA YOU ,  SANG HYUN LEE ,  IN CHAN HWANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L29/417

Abstract: A semiconductor device includes a plurality of active regions spaced apart from each other and extending linearly in parallel on a substrate. A gate electrode crosses the plurality of active regions, and respective drain regions are on and/or in respective ones of the active regions on a first side of the gate electrode and respective source regions are on and/or in respective ones of the active regions on a second side of the gate electrode. A drain plug is disposed on the drain regions and a source plug is disposed on the source regions. A gate plug is disposed on the gate electrode between the drain plug and the source plug such that a straight line passing through a center of the drain plug and a center of the source plug intersects the gate plug.