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    Multi-chip memory system having chip enable function
    4.
    发明授权
    Multi-chip memory system having chip enable function 有权
    具有芯片使能功能的多芯片存储系统

    公开(公告)号：US09589614B2

    公开(公告)日：2017-03-07

    申请号：US14919068

    申请日：2015-10-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chulseung Lee ,  Kyuwook Han ,  Jake Eu

    IPC: G11C5/02 ,  G11C8/06 ,  G11C8/12 ,  G11C16/20 ,  G11C16/08 ,  G11C16/04

    CPC classification number: G11C8/06 ,  G06F2212/7208 ,  G11C8/12 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20

    Abstract: A storage device includes first and second nonvolatile memory groups that respectively include first and second nonvolatile memory chips, a memory controller connected to the first and second nonvolatile memory groups in common through input/output lines and at least one control line, and a group select circuit connected to the memory controller through the at least one control line and chip enable lines. The group select circuit is connected to the first and second nonvolatile memory groups through a plurality of first and second chip enable lines, respectively. The group select circuit, in response to receiving a control signal through the at least one control line, is configured to transmit chip enable signals to a selected memory group among the first nonvolatile memory group and the second nonvolatile memory group through selected chip enable lines among the first chip enable lines and the second chip enable lines.

    Abstract translation: 存储装置包括分别包括第一和第二非易失性存储器芯片的第一和第二非易失性存储器组，通过输入/输出线和至少一个控制线连接到第一和第二非易失性存储器组的存储器控​​制器，以及组选择 电路通过至少一个控制线和芯片使能线连接到存储器控制器。 组选择电路分别通过多个第一和第二芯片使能线连接到第一和第二非易失性存储器组。 组选择电路响应于通过至少一个控制线接收控制信号，被配置为通过所选择的芯片使能线在第一非易失性存储器组和第二非易失性存储器组之间向选定的存储器组发送芯片使能信号， 第一芯片使能线和第二芯片使能线。

    Storage device and data training method thereof
    5.
    发明授权
    Storage device and data training method thereof 有权

    公开(公告)号：US10325633B2

    公开(公告)日：2019-06-18

    申请号：US15962206

    申请日：2018-04-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chulseung Lee ,  ChoongEui Lee ,  Soon Suk Hwang ,  Kyuwook Han

    IPC: G11C11/10 ,  G11C7/10 ,  G11C7/22 ,  G11C29/02 ,  G06F13/16 ,  G11C8/18

    Abstract: Disclosed is a storage device. The storage device includes a nonvolatile memory device that receives write data based on a data strobe signal and a data signal and outputs read data based on the data strobe signal and the data signal, and a controller that performs a training operation for training the nonvolatile memory device to align the data signal and the data strobe signal. The controller detects a left edge of a window of the data signal for the training operation. The controller determines a center of the window by using the detected left edge and unit interval length information of the data signal or determines a start point of a detection operation for detecting a right edge of the window by using the detected left edge and the unit interval length information.

    Delay locked loop, method of operating the same, and memory system including the same
    7.
    发明授权
    Delay locked loop, method of operating the same, and memory system including the same 有权
    延迟锁定环，操作方法和包含相同的存储系统

    公开(公告)号：US09306583B2

    公开(公告)日：2016-04-05

    申请号：US14638363

    申请日：2015-03-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Soon Suk Hwang ,  Youngjin Cho ,  Kyuwook Han ,  Jaegeun Park

    IPC: G11C7/00 ,  H03L7/08 ,  H03L7/085 ,  G11C7/22

    CPC classification number: H03L7/0802 ,  G06F1/04 ,  G06F13/1689 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/085 ,  H03L2207/50 ,  Y02D10/14

    Abstract: A delay locked loop (DLL) is provided. The DLL includes a delay line, a phase detector, a delay line control unit, and a DLL controller. The delay line outputs an output clock by delaying an input clock by a first time on the basis of a select value. The phase detector detects a phase of the output clock. The delay line control unit determines a select value so that the first time corresponds to n periods of the input clock on the basis of the detected phase and an initial select value. The DLL controller provides the initial select value to the delay line control unit. The DLL controller updates the initial select value according to a change of a frequency of the input clock, and to provide the updated initial select value to the delay line control unit.

    Abstract translation: 提供延迟锁定环（DLL）。 DLL包括延迟线，相位检测器，延迟线控制单元和DLL控制器。 延迟线通过基于选择值第一次延迟输入时钟来输出输出时钟。 相位检测器检测输出时钟的相位。 延迟线控制单元确定选择值，使得第一时间基于检测到的相位和初始选择值对应于输入时钟的n个周期。 DLL控制器向延迟线控制单元提供初始选择值。 DLL控制器根据输入时钟频率的变化来更新初始选择值，并向延迟线控制单元提供更新的初始选择值。

    DELAY LOCKED LOOP, METHOD OF OPERATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME
    8.
    发明申请
    DELAY LOCKED LOOP, METHOD OF OPERATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME 有权
    延迟锁定环，其操作方法和包括其的存储系统

    公开(公告)号：US20150256187A1

    公开(公告)日：2015-09-10

    申请号：US14638363

    申请日：2015-03-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SOON SUK HWANG ,  Youngjin Cho ,  Kyuwook Han ,  Jaegeun Park

    IPC: H03L7/08 ,  G11C7/22 ,  H03L7/085

    CPC classification number: H03L7/0802 ,  G06F1/04 ,  G06F13/1689 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/085 ,  H03L2207/50 ,  Y02D10/14

    Abstract: A delay locked loop (DLL) is provided. The DLL includes a delay line, a phase detector, a delay line control unit, and a DLL controller. The delay line outputs an output clock by delaying an input clock by a first time on the basis of a select value. The phase detector detects a phase of the output clock. The delay line control unit determines a select value so that the first time corresponds to n periods of the input clock on the basis of the detected phase and an initial select value. The DLL controller provides the initial select value to the delay line control unit. The DLL controller updates the initial select value according to a change of a frequency of the input clock, and to provide the updated initial select value to the delay line control unit.

    Abstract translation: 提供延迟锁定环（DLL）。 DLL包括延迟线，相位检测器，延迟线控制单元和DLL控制器。 延迟线通过基于选择值第一次延迟输入时钟来输出输出时钟。 相位检测器检测输出时钟的相位。 延迟线控制单元确定选择值，使得第一时间基于检测到的相位和初始选择值对应于输入时钟的n个周期。 DLL控制器向延迟线控制单元提供初始选择值。 DLL控制器根据输入时钟频率的变化来更新初始选择值，并向延迟线控制单元提供更新的初始选择值。

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