公开(公告)号：US20210200634A1

公开(公告)日：2021-07-01

申请号：US17198315

申请日：2021-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHULSEUNG LEE ,  SOON SUK HWANG ,  CHOONGEUI LEE

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C7/10 ,  G11C7/22

Abstract: A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.

公开(公告)号：US20190354431A1

公开(公告)日：2019-11-21

申请号：US16248540

申请日：2019-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHULSEUNG LEE ,  SOON SUK HWANG ,  CHOONGEUI LEE

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C7/10 ,  G11C7/22

Abstract: A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.

公开(公告)号：US20190004984A1

公开(公告)日：2019-01-03

申请号：US15871637

申请日：2018-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHULSEUNG LEE ,  TAESUNG LEE ,  CHOONGEUI LEE ,  SOON SUK HWANG

IPC: G06F13/16 ,  G06F13/12 ,  G06K9/62 ,  G06F15/18

CPC classification number: G06F13/1689 ,  G06F13/126 ,  G06F13/1657 ,  G06K9/6255 ,  G06N20/00

Abstract: A data training method of a storage device, which includes a storage controller and a nonvolatile memory device, includes transmitting a read training command to the nonvolatile memory device, receiving a first training pattern output from the nonvolatile memory device in response to the read training command, receiving a second training pattern output from the nonvolatile memory device in response to the read training command, comparing the received first training pattern and the received second training pattern with a reference pattern, and determining a read timing offset of the storage controller depending on the comparison result.

公开(公告)号：US20220413963A1

公开(公告)日：2022-12-29

申请号：US17900336

申请日：2022-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHULSEUNG LEE ,  SOON SUK HWANG ,  CHOONGEUI LEE

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C7/10 ,  G11C7/22

Abstract: A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.

公开(公告)号：US20180150255A1

公开(公告)日：2018-05-31

申请号：US15804226

申请日：2017-11-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEONGHOON WOO ,  SOON SUK HWANG

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G06F13/28

CPC classification number: G06F3/0635 ,  G06F3/0611 ,  G06F3/064 ,  G06F3/0688 ,  G06F11/1048 ,  G06F11/1068 ,  G06F13/28 ,  G11C29/52 ,  G11C2029/0411

Abstract: A storage device includes nonvolatile memory devices arranged in groups, and a controller connected with the groups respectively through channels. The controller is configured to generate an access request for a nonvolatile memory device among the nonvolatile memory devices, and transmit, based on the access request, access requests respectively to two or more groups, among the groups, respectively through two or more channels, among the channels.

公开(公告)号：US20160180898A1

公开(公告)日：2016-06-23

申请号：US14959106

申请日：2015-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOON SUK HWANG ,  KYU WOOK HAN

IPC: G11C7/10 ,  G06F12/02 ,  G11C16/26

CPC classification number: G11C7/1063 ,  G06F12/0246 ,  G06F13/16 ,  G06F2212/7201 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/1093 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2254

Abstract: A memory controller for controlling a flash memory device is provided. The memory controller generates pattern data, a program command, and a read command, transmits the program command and first data corresponding to the pattern data to the flash memory device so that the first data is programmed to the flash memory device, receives first read data corresponding to the first data, receives a first read data strobe signal, compares the first data with second data corresponding to the first read data, and performs a data training operation according to a comparison result. The first read data and the first read strobe signal are transmitted from the flash memory device in response to the read command.

Abstract translation: 提供一种用于控制闪速存储器件的存储器控​​制器。 存储器控制器产生模式数据，程序命令和读取命令，将程序命令和对应于模式数据的第一数据发送到闪速存储器件，使得第一数据被编程到闪速存储器件，接收第一读取数据 对应于第一数据，接收第一读取数据选通信号，将第一数据与对应于第一读取数据的第二数据进行比较，并根据比较结果执行数据训练操作。 响应于读取命令，从闪存器件发送第一读取数据和第一读取选通信号。

公开(公告)号：US20150256187A1

公开(公告)日：2015-09-10

申请号：US14638363

申请日：2015-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOON SUK HWANG ,  Youngjin Cho ,  Kyuwook Han ,  Jaegeun Park

IPC: H03L7/08 ,  G11C7/22 ,  H03L7/085

CPC classification number: H03L7/0802 ,  G06F1/04 ,  G06F13/1689 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/085 ,  H03L2207/50 ,  Y02D10/14

Abstract: A delay locked loop (DLL) is provided. The DLL includes a delay line, a phase detector, a delay line control unit, and a DLL controller. The delay line outputs an output clock by delaying an input clock by a first time on the basis of a select value. The phase detector detects a phase of the output clock. The delay line control unit determines a select value so that the first time corresponds to n periods of the input clock on the basis of the detected phase and an initial select value. The DLL controller provides the initial select value to the delay line control unit. The DLL controller updates the initial select value according to a change of a frequency of the input clock, and to provide the updated initial select value to the delay line control unit.

Abstract translation: 提供延迟锁定环（DLL）。 DLL包括延迟线，相位检测器，延迟线控制单元和DLL控制器。 延迟线通过基于选择值第一次延迟输入时钟来输出输出时钟。 相位检测器检测输出时钟的相位。 延迟线控制单元确定选择值，使得第一时间基于检测到的相位和初始选择值对应于输入时钟的n个周期。 DLL控制器向延迟线控制单元提供初始选择值。 DLL控制器根据输入时钟频率的变化来更新初始选择值，并向延迟线控制单元提供更新的初始选择值。