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公开(公告)号：US11430779B2
公开(公告)日：2022-08-30
申请号：US17028855
申请日：2020-09-22
发明人： Jaewan Yang , Wootae Kim , Hyungock Kim , Sangdo Park , Jun Seomun
IPC分类号： H01L27/02 , H01L21/768 , H01L27/088 , H01L23/522
摘要： Disclosed are a semiconductor device and a method of fabricating the same. The method includes placing a standard cell, resizing a power via pattern in such a way that the power via pattern has a different width from a width of other via pattern, and applying different design rules to the power via pattern and the other via pattern, respectively, to perform a routing operation on the standard cell.
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公开(公告)号：US09459680B2
公开(公告)日：2016-10-04
申请号：US13948691
申请日：2013-07-23
发明人： Hyungock Kim , Wook Kim , Jun Seomun , Chungki Oh , JaeHan Jeon , Kyungtae Do , JungYun Choi , Hyosig Won , Kee Sup Kim
CPC分类号： G06F1/3206 , G05D23/1919 , G06F1/20 , G06F1/324 , Y02D10/126
摘要： A temperature control method of a semiconductor device is provided. The temperature control method includes detecting a temperature of the semiconductor device; activating a reverse body biasing operation in which a body bias voltage applied to a function block of the semiconductor device is regulated, when the detected temperature is greater than a first temperature level; and activating a thermal throttling operation in which at least one of a frequency of a driving clock provided to a function block of the semiconductor device and a driving voltage applied to the function block of the semiconductor device is regulated, when the detected temperature is greater than a second temperature level that is different than the first temperature level.
摘要翻译： 提供了一种半导体器件的温度控制方法。 温度控制方法包括检测半导体器件的温度; 当检测到的温度大于第一温度水平时，激活施加到半导体器件的功能块的体偏置电压的反向体偏置操作; 以及激活热调节操作，其中当检测到的温度大于所述热节流操作时，提供给所述半导体器件的功能块的驱动时钟的频率中的至少一个和施加到所述半导体器件的功能块的驱动电压被调节 与第一温度水平不同的第二温度水平。
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公开(公告)号：US20230325571A1
公开(公告)日：2023-10-12
申请号：US18149749
申请日：2023-01-04
发明人： Juyeon Kim , Jaehoon Kim , Sun Ik Heo , Jun Seomun , Hyun-Seung Seo , Chul Rim , Chang Ho Han
IPC分类号： G06F30/392
CPC分类号： G06F30/392 , G06F2119/12
摘要： A cell library is provided. The cell library is stored in a computer-readable storage medium. The cell library is configured to store: first delay information of a standard cell according to a threshold voltage of a transistor included in the standard cell; and second delay information of the standard cell according to mobility of the transistor included in the standard cell.
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公开(公告)号：US09984732B2
公开(公告)日：2018-05-29
申请号：US15436234
申请日：2017-02-17
发明人： Jun Seomun , Insub Shin , Kyungtae Do , JungYun Choi
CPC分类号： G11C7/1012 , G11C5/143 , G11C7/10 , G11C7/222
摘要： Voltage monitors include a predelay cell having an input responsive to a first clock signal. This cell is configured to generate a predelayed clock signal at an output thereof. A serially-connected string of data delay cells is provided, which has an input responsive to the predelayed clock signal. A serially-connected string of clock delay cells is provided, which has an input responsive to a second clock signal that is synchronized to the first clock signal. A plurality latches are provided. The latches have respective data inputs, which are responsive to first periodic signals generated at respective outputs of the serially-connected string of data delay cells, and respective clock/sync terminals, which are responsive to second periodic signals generated at respective outputs of the serially-connected string of clock delay cells. The latches enable loading of a delay code value, which indicates power supply voltage variation.
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公开(公告)号：US11646305B2
公开(公告)日：2023-05-09
申请号：US16946620
申请日：2020-06-30
发明人： Sungok Lee , Sangdo Park , Jun Seomun , Bonghyun Lee
CPC分类号： H01L27/0207
摘要： Semiconductor devices may include standard cells arranged in a first direction and a second direction intersecting the first direction. Both the first and second directions may be parallel to an upper surface of the substrate. Each of the standard cells may include semiconductor elements. The semiconductor device may also include filler cells between two standard cells, and each of the filler cells may include a filler active region and a filler contact connected to the filler active region and may extend in the first direction. The semiconductor device may further include a lower wiring pattern electrically connected to at least one of the semiconductor elements and may extend into at least one of the filler cells in the second direction, and the filler contacts may include wiring filler contacts lower than the lower wiring pattern and connected to at least one of the lower wiring pattern.
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公开(公告)号：US11270992B2
公开(公告)日：2022-03-08
申请号：US16992422
申请日：2020-08-13
发明人： Jaehoon Kim , Jun Seomun , Sua Lee , Hyungock Kim
IPC分类号： H01L27/02 , H01L23/528 , H01L29/78 , H01L29/06 , H01L29/423 , H01L29/786 , G06F30/392 , G06F30/394 , G06F30/398 , G06F115/12
摘要： A semiconductor device includes standard cells disposed in a first direction parallel to an upper surface of a substrate and a second direction intersecting the first direction, each standard cell including an active region, a gate structure disposed to intersect the active region, source/drain regions on the active region at both sides of the gate structure, and first interconnection lines electrically connected to the active region and the gate structures; filler cells disposed between at least portions of the standard cells, each filler cell including a filler active region and a filler gate structure disposed to intersect the filler active region; and a routing structure disposed on the standard cells and the filler cells and including second interconnection lines electrically connecting the first interconnection lines of different standard cells to each other, wherein the second interconnection lines includes a first line having a first width and a second line having a second width larger than the first width.
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