公开(公告)号：US20240347597A1

公开(公告)日：2024-10-17

申请号：US18517893

申请日：2023-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINWOO LEE ,  YOUNGKYOU SHIN ,  SUTAE KIM

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including an active pattern, a first semiconductor pattern on the active pattern, and gate electrodes extending in a first direction and arranged in a second direction intersecting the first direction. A first top surface of the first semiconductor pattern includes first and second corners spaced apart from each other in the first direction. The first top surface of the first semiconductor pattern includes a first portion connecting the first and second corners. A length of the first portion of the first semiconductor pattern is greater than a distance in the first direction between the first corner and the second corner.

公开(公告)号：US20200075853A1

公开(公告)日：2020-03-05

申请号：US16364232

申请日：2019-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNG-GEUN YU ,  ZHU WU ,  JA BIN LEE ,  JUNG MOO LEE ,  JINWOO LEE ,  KYUBONG JUNG

IPC: H01L45/00 ,  H01L27/24

Abstract: A switching element includes a lower barrier electrode on a substrate, a switching pattern on the lower barrier electrode, and an upper barrier electrode on the switching pattern. The lower barrier electrode includes a first lower barrier electrode layer, and a second lower barrier electrode layer interposed between the first lower barrier electrode layer and the switching pattern and whose density is different from the density of the first lower barrier electrode.

公开(公告)号：US20230232640A1

公开(公告)日：2023-07-20

申请号：US17931116

申请日：2022-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINWOO LEE ,  DONGHO AHN ,  DONGGEON GU ,  WONJUN PARK ,  CHANGYUP PARK

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/249 ,  H01L45/1683

Abstract: A variable resistance memory device includes a stacking pattern disposed on a substrate, a vertical structure extends in a first direction, which is perpendicular to a top surface of the substrate, and penetrates the stacking pattern, and a horizontal conductive line disposed adjacent to the stacking pattern and extending in a second direction that is parallel to the top surface of the substrate. The vertical structure includes a vertical conductive line penetrating the stacking pattern, a variable resistance element enclosing the vertical conductive line, and a selection element interposed between the vertical conductive line and the variable resistance element. Each of the vertical conductive line, the variable resistance element, and the selection element extends in the first direction. The stacking pattern is electrically connected to the horizontal conductive line and extends along the horizontal conductive line and in the second direction.

公开(公告)号：US20250081865A1

公开(公告)日：2025-03-06

申请号：US18818913

申请日：2024-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINWOO LEE ,  Hyunsang Hwang ,  Youngdong Kim ,  DONGHO AHN ,  Jin Myung Choi ,  Geon Hui Han

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

Abstract: A memory device comprising a stacking structure including a plurality of electrodes and an insulation layer between the plurality of electrodes. The stacking structure has a recess portion corresponding to the plurality of electrodes or the insulation layer at a side surface of the stacking structure. The memory device also comprising a resistance variable layer on the side surface of the stacking structure having the recess portion, and includes a portion extending in an extension direction crossing the stacking structure. The resistance variable layer includes a first portion including a first expanded portion along a recess surface of the recess portion, a second portion including a second expanded portion along the recess surface of the recess portion on the first portion, and a third portion on the second portion. The second portion has a resistance smaller than a resistance of the first portion.

公开(公告)号：US20240175915A1

公开(公告)日：2024-05-30

申请号：US18203138

申请日：2023-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEKYE JEON ,  JINWOO LEE ,  JONGCHEON SUN ,  SUYOUNG LEE ,  HYEONGCHEOL LEE ,  CHUNGSAM JUN

IPC: G01R31/28

CPC classification number: G01R31/2853 ,  G01R31/287

Abstract: In a substrate inspection method, a substrate is provided on a substrate stage, the substrate having internal wires and connection wires, the internal wires respectively provided between stacked insulating layers, the connection wires respectively extending from the internal wires and exposed to an upper surface of the substrate. An electric circuit of the internal wires in the substrate is modeled to generate a circuit model. AC power is applied to the substrate stage to obtain measured capacitance values of the internal wires through currents that are obtained from the connection wires. DC power is applied to the substrate stage to obtain measured resistance values of the internal wires through voltages that are obtained from the connection wires. Impedance values of the internal wires are calculated through the measured capacitance values and the measured resistance values. The impedance values and the circuit model are compared to determine reliability of the substrate.

公开(公告)号：US20230079697A1

公开(公告)日：2023-03-16

申请号：US17868401

申请日：2022-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINWOO LEE ,  YUNSE OH ,  BYUNG-SUNG KIM ,  SUTAE KIM ,  Seung CHOI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Disclosed is a semiconductor device including: a substrate including a first active pattern separated into a pair of first active patterns by a trench; a device isolation layer filling the trench; first source/drain patterns on the first active pattern; a first channel pattern connected to the first source/drain patterns and including semiconductor patterns; a first dummy gate electrode that extends while being adjacent to a first sidewall of the trench; a gate electrode that is spaced apart in the first direction from the first dummy gate electrode and extends while running across the first channel pattern, a gate capping pattern on the gate electrode; a gate contact coupled to the gate electrode; and a separation pattern extending between the gate electrode and the first dummy gate electrode. A top surface of the separation pattern is at a same level as that of the gate capping pattern.