公开(公告)号：US20250081865A1

公开(公告)日：2025-03-06

申请号：US18818913

申请日：2024-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINWOO LEE ,  Hyunsang Hwang ,  Youngdong Kim ,  DONGHO AHN ,  Jin Myung Choi ,  Geon Hui Han

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

Abstract: A memory device comprising a stacking structure including a plurality of electrodes and an insulation layer between the plurality of electrodes. The stacking structure has a recess portion corresponding to the plurality of electrodes or the insulation layer at a side surface of the stacking structure. The memory device also comprising a resistance variable layer on the side surface of the stacking structure having the recess portion, and includes a portion extending in an extension direction crossing the stacking structure. The resistance variable layer includes a first portion including a first expanded portion along a recess surface of the recess portion, a second portion including a second expanded portion along the recess surface of the recess portion on the first portion, and a third portion on the second portion. The second portion has a resistance smaller than a resistance of the first portion.