公开(公告)号：US20210183757A1

公开(公告)日：2021-06-17

申请号：US17017638

申请日：2020-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  Hyunkyu Kim ,  Jongbo Shim ,  Eunhee Jung ,  Kyoungsei Choi

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

公开(公告)号：US20240178114A1

公开(公告)日：2024-05-30

申请号：US18227348

申请日：2023-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK ,  DONGKYU KIM ,  JI HWANG KIM ,  HYEONJEONG HWANG

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/565 ,  H01L21/568 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16055 ,  H01L2224/16227 ,  H01L2224/32146 ,  H01L2224/32235 ,  H01L2924/1435 ,  H01L2924/15311 ,  H01L2924/351

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a lower semiconductor chip on a first redistribution substrate and including a through via, a lower molding layer on the first redistribution substrate and surrounding the lower semiconductor chip, a lower post on the first redistribution substrate and laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and coupled to the through via, an upper molding layer on the lower molding layer and surrounding the upper semiconductor chip, an upper post on the lower molding layer and laterally spaced apart from the upper semiconductor chip, and a second redistribution substrate on the upper molding layer and coupled to the upper post. A top surface of the lower molding layer is at a level higher than that of a top surface of the lower semiconductor chip.

公开(公告)号：US20210043612A1

公开(公告)日：2021-02-11

申请号：US16845567

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： JANGWOO LEE ,  JONGBO SHIM ,  JI HWANG KIM ,  YUNGCHEOL KONG ,  YOUNGBAE KIM ,  TAEHWAN KIM ,  HYUNGLAK MA

IPC: H01L25/10 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package device may include a first package substrate, a first semiconductor chip on the first package substrate, an interposer on the first semiconductor chip, a warpage prevention member on the interposer, a molding member on the interposer and the first package substrate, and a second package substrate on the molding member. At least a portion of a top surface of the molding member may be spaced apart from a bottom surface of the second package substrate.

公开(公告)号：US20200020647A1

公开(公告)日：2020-01-16

申请号：US16198978

申请日：2018-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG KUN JEE ,  JI HWANG KIM ,  UN BYOUNG KANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/29

Abstract: A semiconductor chip module includes a chip package and a printed circuit board (PCB) to which the chip package is mounted. The chip package includes a substrate, a processor disposed in a central region of the substrate, a plurality of active chips disposed around the processor, a plurality of dummy chips disposed in spaces between the plurality of active chips, and an epoxy resin fixing the plurality of active chips and the plurality of dummy chips to the substrate. Channels of the epoxy resin extend between an uppermost surface of a chip body of each of the dummy chips and the substrate of the chip package to control or mitigate warping of the chip package.

公开(公告)号：US20190333957A1

公开(公告)日：2019-10-31

申请号：US16507623

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  CHAJEA JO ,  HYOEUN KIM ,  JONGBO SHIM ,  SANG-UK HAN

IPC: H01L27/146 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.

公开(公告)号：US20230260891A1

公开(公告)日：2023-08-17

申请号：US18308433

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  HYUNKYU KIM ,  JONGBO SHIM ,  EUNHEE JUNG ,  KYOUNGSEL CHOI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/45 ,  H01L25/0657

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

公开(公告)号：US20220115281A1

公开(公告)日：2022-04-14

申请号：US17350329

申请日：2021-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  DONGHO KIM ,  JIN-WOO PARK ,  JONGBO SHIM

IPC: H01L23/13 ,  H01L25/10 ,  H01L21/48 ,  H01L25/00

Abstract: A semiconductor package includes: a lower package: an upper substrate on the lower package: and connection members connecting the lower package to the upper substrate. wherein the lower package includes: a lower substrate; and a lower semiconductor chip, wherein the upper substrate includes: an upper substrate body: upper connection pads combined with the connection members: and auxiliary members extending from the upper substrate body toward the lower substrate, wherein the connection members are arranged in a first horizontal direction to form a first connection member column, wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, and the first auxiliary member column is spaced apart from the first connection member column.

公开(公告)号：US20240243053A1

公开(公告)日：2024-07-18

申请号：US18457535

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  JOONSUNG KIM ,  SANGJIN BAEK ,  KYOUNG LIM SUK

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/165 ,  H01L2225/06517

Abstract: A semiconductor package includes a first redistribution layer; a first semiconductor chip above the first redistribution layer; a second semiconductor chip above the first semiconductor chip; a second redistribution layer above the second semiconductor chip; a first connection structure on the second redistribution layer; a connection post on the first connection structure; and a connection interconnection layer on the connection post, wherein the connection interconnection layer comprises a connection insulating layer and a connection via extending through the connection insulating layer, and wherein the second redistribution layer and the first redistribution layer are electrically connected to each other through a wire.

公开(公告)号：US20220319973A1

公开(公告)日：2022-10-06

申请号：US17807894

申请日：2022-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  HYUNKYU KIM ,  JONGBO SHIM ,  EUNHEE JUNG ,  KYOUNGSEI CHOI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

公开(公告)号：US20220165680A1

公开(公告)日：2022-05-26

申请号：US17501008

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONG HO KIM ,  JI HWANG KIM ,  HWAN PIL PARK ,  JONG BO SHIM

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/42 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern; a first semiconductor chip placed on an upper surface of the first substrate; a ball array structure that is placed on the upper surface of the first substrate along a perimeter of the first semiconductor chip and is electrically connected to the ground pattern; and a shielding structure placed on the upper surface of the first semiconductor chip and in contact with the upper surface of the ball array structure. The ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions. A maximum width of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion.