-
1.
公开(公告)号:US10354985B2
公开(公告)日:2019-07-16
申请号:US15438184
申请日:2017-02-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Won-Gi Chang , Dongwon Lee , Myung-Sung Kang , Hyein Yoo
IPC: H01L21/56 , H01L25/00 , H01L21/78 , H01L23/00 , H01L25/065
Abstract: A method for manufacturing a semiconductor device includes stacking, on a package substrate, first semiconductor chips. Each of the first semiconductor chips includes a first adhesive film. The method includes stacking, respectively on the first semiconductor chips, second semiconductor chips. Each of the second semiconductor chips includes a second adhesive film. The method includes compressing the first and second adhesive films to form an adhesive structure. The adhesive structure includes an extension disposed on sidewalls of the first and second semiconductor chips. The method includes removing the extension. The method includes forming a first molding layer substantially covering the first and second semiconductor chips. The method includes performing a cutting process on the package substrate between the first and second semiconductor chips to form a plurality of semiconductor packages each including at least one of the first semiconductor chips and at least one of the second semiconductor chips.
-
2.
公开(公告)号:US11355413B2
公开(公告)日:2022-06-07
申请号:US16540495
申请日:2019-08-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Joungphil Lee , Myung-Sung Kang , Yeongseok Kim , Gwangsun Seo , Hyein Yoo , Yongwon Choi
IPC: C09J7/28 , C09J11/04 , H01L23/373 , H01L23/29 , H01L23/00 , H01L23/31 , H01L23/538 , H01L23/367
Abstract: An adhesive film includes a porous metal layer having a plurality of pores therein, a first adhesive layer on one side of the porous metal layer, an adhesive substance at least partially filling the pores of the porous metal layer, and a plurality of first thermal conductive members distributed in the first adhesive layer.
-
3.
公开(公告)号:US20190273075A1
公开(公告)日:2019-09-05
申请号:US16417934
申请日:2019-05-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Won-Gi Chang , Dongwon Lee , Myung-Sung Kang , Hyein Yoo
IPC: H01L25/00 , H01L25/065 , H01L23/00 , H01L21/78 , H01L21/56
Abstract: A method for manufacturing a semiconductor device includes stacking, on a package substrate, first semiconductor chips. Each of the first semiconductor chips includes a first adhesive film. The method includes stacking, respectively on the first semiconductor chips, second semiconductor chips. Each of the second semiconductor chips includes a second adhesive film. The method includes compressing the first and second adhesive films to form an adhesive structure. The adhesive structure includes an extension disposed on sidewalls of the first and second semiconductor chips. The method includes removing the extension. The method includes forming a first molding layer substantially covering the first and second semiconductor chips. The method includes performing a cutting process on the package substrate between the first and second semiconductor chips to form a plurality of semiconductor packages each including at least one of the first semiconductor chips and at least one of the second semiconductor chips.
-
4.
公开(公告)号:US10147713B2
公开(公告)日:2018-12-04
申请号:US15889957
申请日:2018-02-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyein Yoo , Yeongseok Kim
IPC: H01L25/00 , H01L21/56 , H01L21/78 , H01L23/31 , H01L25/065 , H01L23/552
Abstract: A method of fabricating a semiconductor package includes mounting a plurality of semiconductor chips on a substrate in a stripped state, forming a mold layer to cover the semiconductor chips, cutting the mold layer and the substrate to form unit packages separated from each other, and forming a shielding layer on the mold layer of each of the unit packages, wherein each of the unit packages includes a corresponding one of the semiconductor chips, wherein the mold layer in each of the unit packages includes side surfaces, a top surface, and corner regions, and wherein each of the corner regions of the mold layer includes a first corner, which is connected to a corresponding one of the side surfaces and has a first curvature radius, and a second corner, which is connected to the top surface and has a second curvature radius smaller than the first curvature radius.
-
公开(公告)号:US12183653B2
公开(公告)日:2024-12-31
申请号:US17726916
申请日:2022-04-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Joungphil Lee , Myung-Sung Kang , Yeongseok Kim , Gwangsun Seo , Hyein Yoo , Yongwon Choi
IPC: H01L23/373 , C09J7/28 , C09J11/04 , H01L23/00 , H01L23/29 , H01L23/31 , H01L23/367 , H01L23/538
Abstract: An adhesive film includes a porous metal layer having a plurality of pores therein, a first adhesive layer on one side of the porous metal layer, an adhesive substance at least partially filling the pores of the porous metal layer, and a plurality of first thermal conductive members distributed in the first adhesive layer.
-
6.
公开(公告)号:US10923465B2
公开(公告)日:2021-02-16
申请号:US16417934
申请日:2019-05-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Won-Gi Chang , Dongwon Lee , Myung-Sung Kang , Hyein Yoo
IPC: H01L25/00 , H01L21/683 , H01L21/56 , H01L23/31 , H01L23/00 , H01L21/78 , H01L25/065
Abstract: A method for manufacturing a semiconductor device includes stacking, on a package substrate, first semiconductor chips. Each of the first semiconductor chips includes a first adhesive film. The method includes stacking, respectively on the first semiconductor chips, second semiconductor chips. Each of the second semiconductor chips includes a second adhesive film. The method includes compressing the first and second adhesive films to form an adhesive structure. The adhesive structure includes an extension disposed on sidewalls of the first and second semiconductor chips. The method includes removing the extension. The method includes forming a first molding layer substantially covering the first and second semiconductor chips. The method includes performing a cutting process on the package substrate between the first and second semiconductor chips to form a plurality of semiconductor packages each including at least one of the first semiconductor chips and at least one of the second semiconductor chips.
-
公开(公告)号:US10115613B2
公开(公告)日:2018-10-30
申请号:US15470606
申请日:2017-03-27
Applicant: Samsung Electronics Co., Ltd.
Inventor: Won-Gi Chang , Yeongseok Kim , Hyein Yoo
Abstract: The present disclosure relates to a method of fabricating a semiconductor package. The method may include forming a cavity in a package substrate and providing the package substrate and a die on a carrier tape film. Here, the carrier tape film may include a tape substrate and an insulating layer on the tape substrate, and the die may be provided in the cavity of the package substrate. The method may further include subsequently forming an encapsulation layer to cover the insulating layer and the die in the cavity and cover the package substrate on the insulating layer and removing the tape substrate from the insulating layer.
-
公开(公告)号:US09929131B2
公开(公告)日:2018-03-27
申请号:US15355476
申请日:2016-11-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyein Yoo , Yeongseok Kim
IPC: H01L25/00 , H01L21/56 , H01L21/78 , H01L23/31 , H01L25/065
CPC classification number: H01L25/50 , H01L21/561 , H01L21/565 , H01L21/78 , H01L23/3128 , H01L23/552 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06524 , H01L2225/06537 , H01L2225/06568 , H01L2225/06589 , H01L2924/15311 , H01L2924/1815 , H01L2924/3025 , H01L2924/00012 , H01L2924/00014 , H01L2224/83 , H01L2224/85 , H01L2924/00
Abstract: A method of fabricating a semiconductor package includes mounting a plurality of semiconductor chips on a substrate in a stripped state, forming a mold layer to cover the semiconductor chips, cutting the mold layer and the substrate to form unit packages separated from each other, and forming a shielding layer on the mold layer of each of the unit packages, wherein each of the unit packages includes a corresponding one of the semiconductor chips, wherein the mold layer in each of the unit packages includes side surfaces, a top surface, and corner regions, and wherein each of the corner regions of the mold layer includes a first corner, which is connected to a corresponding one of the side surfaces and has a first curvature radius, and a second corner, which is connected to the top surface and has a second curvature radius smaller than the first curvature radius.
-
-
-
-
-
-
-