公开(公告)号：US20160276342A1

公开(公告)日：2016-09-22

申请号：US14988039

申请日：2016-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Me LIM ,  Young-Dal LIM ,  Hag-Ju CHO

IPC: H01L27/088 ,  H01L29/423 ,  H01L27/12 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/42356 ,  H01L29/785

Abstract: Semiconductor devices including STI liners are provided. The semiconductor devices may include a STI trench that defines an active region in a substrate, a STI liner that extends conformally along side walls and a bottom surface of the STI trench, a device isolation film that is on the STI liner and fills up at least a part of the STI trench, a first gate structure that is disposed on the active region, and a second gate structure that is spaced apart from the first gate structure. The second gate structure may include a gate insulating film contacting the device isolation film, a gate electrode on the gate insulating film, and spacers on both sides of the gate electrode. Lower surfaces of the spacers may contact an upper surface of the STI liner.

Abstract translation: 提供包括STI衬垫的半导体器件。 半导体器件可以包括限定衬底中的有源区的STI沟槽，沿侧壁和STI沟槽的底表面共形延伸的STI衬垫，STI衬套上的器件隔离膜，至少填满 STI沟槽的一部分，设置在有源区上的第一栅极结构和与第一栅极结构间隔开的第二栅极结构。 第二栅极结构可以包括与器件隔离膜接触的栅极绝缘膜，栅极绝缘膜上的栅极电极和栅电极两侧的间隔物。 间隔件的下表面可接触STI衬套的上表面。

公开(公告)号：US20130316514A1

公开(公告)日：2013-11-28

申请号：US13956482

申请日：2013-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Pil KIM ,  Young-Goan JANG ,  Dong-Won KIM ,  Hag-Ju CHO

IPC: H01L21/28 ,  H01L21/76

CPC classification number: H01L21/28008 ,  H01L21/28123 ,  H01L21/76 ,  H01L21/76232 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.

Abstract translation: 制造栅极的方法包括在基板的基本上整个表面上依次形成绝缘层和导电层。 衬底在其中具有器件隔离层，器件隔离层的顶表面高于衬底的顶表面。 该方法包括通过图案化绝缘层和导电层来平坦化导电层的顶表面并形成栅电极。