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    STACKED STRUCTURE INCLUDING CONDUCTIVE PATTERN FOR SELF-ALIGNMENT
    1.
    发明申请
    STACKED STRUCTURE INCLUDING CONDUCTIVE PATTERN FOR SELF-ALIGNMENT 有权

    公开(公告)号：US20240404936A1

    公开(公告)日：2024-12-05

    申请号：US18417921

    申请日：2024-01-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Gyujin Choi ,  Dahee Kim ,  Jae-Ean Lee ,  Taehoon Lee

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065

    Abstract: A stacked structure includes a lower substrate and a first semiconductor chip stacked on an upper surface of the lower substrate, the lower substrate includes a lower conductor pattern disposed on the upper surface of the lower substrate, the first semiconductor chip may have first and second surfaces facing each other, the second surface of the first semiconductor chip may face the upper surface of the lower substrate, and the first semiconductor chip may include a first conductor pattern disposed on the second surface. The first conductor pattern may be aligned with the lower conductor pattern in a first direction perpendicular to the upper surface of the lower substrate, and the first conductor pattern may be spaced apart from the lower conductor pattern in the first direction.

    SEMICONDUCTOR PACKAGE DEVICE
    2.
    发明申请
    SEMICONDUCTOR PACKAGE DEVICE 有权

    公开(公告)号：US20220384324A1

    公开(公告)日：2022-12-01

    申请号：US17568465

    申请日：2022-01-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Gyujin Choi ,  Jae-Ean Lee ,  Changeun Joo

    IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31

    Abstract: Disclosed is a semiconductor package device comprising a semiconductor chip including first and second chip pads on an active surface of the semiconductor chip, and a redistribution substrate on the first and second chip pads. The redistribution substrate includes first and second redistribution patterns sequentially stacked on the active surface. The first redistribution pattern includes a first via part and a first via pad part vertically overlapping the first via part. The second redistribution pattern includes a second via part and a second via pad part vertically overlapping the second via part. The first via part contacts the first chip pad. The second via part contacts the second chip pad. A length of the second via part is greater than that of the first via part.

    Semiconductor packages having vias
    5.
    发明授权
    Semiconductor packages having vias 有权

    公开(公告)号：US11587898B2

    公开(公告)日：2023-02-21

    申请号：US16947093

    申请日：2020-07-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changeun Joo ,  Gyujin Choi

    IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00

    Abstract: A semiconductor package includes a lower redistribution layer including an insulating pattern having an opening and a via in the opening; a first semiconductor chip including a chip pad, a passivation layer, and a pad bump connected to the chip pad; and a first encapsulant on the lower redistribution layer and the first semiconductor chip. The opening defines a lower surface and a side surface of the pad bump, and the via is in physical contact with the lower surface and the side surface of the pad bump.

    Semiconductor package
    8.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11810864B2

    公开(公告)日：2023-11-07

    申请号：US17849938

    申请日：2022-06-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Changeun Joo ,  Gyujin Choi

    IPC: H01L23/538 ,  H01L23/498 ,  H01L21/56

    CPC classification number: H01L23/5386 ,  H01L23/49816 ,  H01L23/5383 ,  H01L21/565

    Abstract: A semiconductor package includes a core substrate having a through hole, a first molding member at least partially filling the through hole and covering an upper surface of the core substrate, the first molding member having a cavity within the through hole, a first semiconductor chip on the first molding member on the upper surface of the core substrate, a second semiconductor chip arranged within the cavity, a second molding member on the first molding member and covering the first semiconductor chip, a third molding member filling the cavity and covering the lower surface of the core substrate; first redistribution wirings on the second molding member and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate; and second redistribution wirings on the third molding member and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings.

    SEMICONDUCTOR PACKAGE
    9.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20240387486A1

    公开(公告)日：2024-11-21

    申请号：US18584905

    申请日：2024-02-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dahee Kim ,  Hongwon Kim ,  Jae-Ean Lee ,  Taehoon Lee ,  Gyujin Choi

    IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

    Abstract: An example semiconductor package includes a substrate, a first semiconductor chip mounted on the substrate, a mold layer on the substrate to cover the first semiconductor chip, and outer terminals positioned below the substrate. The substrate includes a first interconnection layer, a second interconnection layer on the first interconnection layer, a passive device mounted on a bottom surface of the second interconnection layer, and a connection member at a side of the passive device and between the first interconnection layer and the second interconnection layer to connect the first interconnection layer to the second interconnection layer. The outer terminals are coupled to a bottom surface of the first interconnection layer, the passive device includes a first pad on a top surface of the passive device, and an interconnection pattern of the second interconnection layer contacts the first pad.

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