公开(公告)号：US11728283B2

公开(公告)日：2023-08-15

申请号：US17183513

申请日：2021-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chilwoo Kwon ,  Jeongseok Kim ,  Junggon Choi

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L23/64

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/30111 ,  H01L2924/3511

Abstract: A package substrate may include a plurality of stacked insulation layers, a plurality of RDLs and a pair of impedance patterns. The RDLs may be arranged between the insulation layers. The impedance patterns may be arranged on an upper surface of at least one of the insulation layers. The impedance patterns may have an insulation length corresponding to a summed length of thicknesses of at least two insulation layers among the plurality of the insulation layers. Thus, a dummy conductive pattern may not be arranged between the impedance patterns and the RDL so that only the insulation layer may exist between the impedance patterns and the RDL. As a result, the insulation length of the impedance patterns may correspond to the summed length of the thicknesses of the at least two insulation layers.

公开(公告)号：US11264339B2

公开(公告)日：2022-03-01

申请号：US16703239

申请日：2019-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyujin Choi ,  Sunghoan Kim ,  Changeun Joo ,  Chilwoo Kwon ,  Youngkyu Lim ,  Sunguk Lee

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: The method of manufacturing a connection structure of a semiconductor chip includes: preparing a semiconductor chip having a first surface having a connection pad disposed thereon and a second surface opposing the first surface and including a passivation layer disposed on the first surface and covering the connection pad; forming an insulating layer on the first surface of the semiconductor chip, the insulating layer covering at least a portion of the passivation layer; forming a via hole penetrating through the insulating layer to expose at least a portion of the passivation layer; exposing at least a portion of the connection pad by removing the passivation layer exposed by the via hole; forming a redistribution via by filling the via hole with a conductive material; and forming a redistribution layer on the redistribution via and the insulating layer.

公开(公告)号：US10985091B2

公开(公告)日：2021-04-20

申请号：US16691910

申请日：2019-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyeun Choi ,  Jaemok Jung ,  Eunjin Kim ,  Chilwoo Kwon

IPC: H01L23/495 ,  H01L23/28 ,  H01L23/522

Abstract: This invention provides a semiconductor package, the semiconductor package includes: a semiconductor chip having a connection pad; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the semiconductor chip and the encapsulant. The connection structure comprises a first insulation layer, a first redistribution layer disposed on the first insulation layer, and a second insulation layer disposed on the first insulation layer and covering the first redistribution layer. The first redistribution layer has one or more openings. The openings have a shape having a plurality of protrusions, respectively, and B/A is 1.5 or less, where A refers to a thickness of the first redistribution layer, and B refers to a thickness of a region of the second insulation layer covering the first redistribution layer.