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    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220352156A1

    公开(公告)日：2022-11-03

    申请号：US17846177

    申请日：2022-06-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunyoung NOH ,  Wandon KIM ,  Hyunbae LEE ,  Donggon YOO ,  Dong-Chan LIM

    IPC: H01L27/088 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/535

    Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210066289A1

    公开(公告)日：2021-03-04

    申请号：US16851476

    申请日：2020-04-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunyoung NOH ,  Wandon KIM ,  Hyunbae LEE ,  Donggon YOO ,  Dong-Chan LIM

    IPC: H01L27/088 ,  H01L23/528 ,  H01L23/532 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/768 ,  H01L29/06

    Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

    SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURED USING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURED USING THE SAME 有权

    公开(公告)号：US20240395745A1

    公开(公告)日：2024-11-28

    申请号：US18433177

    申请日：2024-02-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun Kyoung LEE ,  Tae Seong KIM ,  Ho-Jin LEE ,  Dong-Chan LIM ,  Jae Won HWANG

    IPC: H01L23/00 ,  H01L27/146

    Abstract: The present disclosure provides a semiconductor device manufacturing method that includes forming a lower chip and an upper chip, and bonding the lower chip and the upper chip to each other. The forming of the lower chip includes providing a lower substrate, sequentially forming a lower interlayer insulating film and a pre-lower adhesive film, etching portions of the pre-lower adhesive film and the lower interlayer insulating film to form a lower trench, forming, using a sputtering process, a first lower seed film and a second lower seed film. The forming of the upper chip includes providing an upper substrate, sequentially forming an upper interlayer insulating film and a pre-upper adhesive film, etching portions of the pre-upper adhesive film and the upper interlayer insulating film to form an upper trench, forming, using the sputtering process, a first upper seed film and a second upper seed film.

    METHODS OF FORMING A SEMICONDUCTOR DEVICE
    8.
    发明申请
    METHODS OF FORMING A SEMICONDUCTOR DEVICE 审中-公开
    形成半导体器件的方法

    公开(公告)号：US20130337647A1

    公开(公告)日：2013-12-19

    申请号：US13971991

    申请日：2013-08-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Deok-Young JUNG ,  Gil-Heyun CHOI ,  Suk-Chul BANG ,  Byung-Lyul PARK ,  Kwang-Jin MOON ,  Dong-Chan LIM

    IPC: H01L21/768

    CPC classification number: H01L21/76802 ,  H01L21/02057 ,  H01L21/30655 ,  H01L21/76814 ,  H01L21/76898

    Abstract: The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern.

    Abstract translation: 所述方法包括通过蚀刻半导体衬底形成半导体衬底图案。 半导体图案具有暴露半导体衬底图案的侧壁的第一通孔，并且由第一通孔露出的半导体衬底图案的侧壁具有杂质层图案。 所述方法还包括处理半导体衬底图案的上表面，所处理的半导体衬底图案的上表面是疏水的; 从由第一通孔露出的半导体衬底图案的侧壁去除杂质层图案; 在由第一通孔露出的半导体衬底图案的侧壁上形成第一绝缘层图案; 以及将第一导电层图案填充到第一通孔中并在第一绝缘层图案之上。

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