公开(公告)号：US20130337647A1

公开(公告)日：2013-12-19

申请号：US13971991

申请日：2013-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deok-Young JUNG ,  Gil-Heyun CHOI ,  Suk-Chul BANG ,  Byung-Lyul PARK ,  Kwang-Jin MOON ,  Dong-Chan LIM

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/02057 ,  H01L21/30655 ,  H01L21/76814 ,  H01L21/76898

Abstract: The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern.

Abstract translation: 所述方法包括通过蚀刻半导体衬底形成半导体衬底图案。 半导体图案具有暴露半导体衬底图案的侧壁的第一通孔，并且由第一通孔露出的半导体衬底图案的侧壁具有杂质层图案。 所述方法还包括处理半导体衬底图案的上表面，所处理的半导体衬底图案的上表面是疏水的; 从由第一通孔露出的半导体衬底图案的侧壁去除杂质层图案; 在由第一通孔露出的半导体衬底图案的侧壁上形成第一绝缘层图案; 以及将第一导电层图案填充到第一通孔中并在第一绝缘层图案之上。

公开(公告)号：US20130140697A1

公开(公告)日：2013-06-06

申请号：US13685174

申请日：2012-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kun-Sang Park ,  Byung-Lyul PARK ,  Su-Kyoung KIM ,  Kwang-Jin MOON ,  Suk-Chul BANG ,  Do-Sun LEE ,  Dong-Chan LIM ,  Gil-Heyun CHOI

IPC: H01L23/00

CPC classification number: H01L24/28 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0655 ,  H01L2224/05009 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/0903 ,  H01L2224/8001 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: Provided are electrode-connecting structures or semiconductor devices, including a lower device including a lower substrate, a lower insulating layer formed on the lower substrate, and a lower electrode structure formed in the lower insulating layer, wherein the lower electrode structure includes a lower electrode barrier layer and a lower metal electrode formed on the lower electrode barrier layer, and an upper device including an upper substrate, an upper insulating layer formed under the upper substrate, and an upper electrode structure formed in the upper insulating layer, wherein the upper electrode structure includes an upper electrode barrier layer extending from the inside of the upper insulating layer under a bottom surface thereof and an upper metal electrode formed on the upper electrode barrier layer. The lower metal electrode is in direct contact with the upper metal electrode.

Abstract translation: 提供了电极连接结构或半导体器件，包括下部器件，包括下部衬底，形成在下部衬底上的下部绝缘层和形成在下部绝缘层中的下部电极结构，其中下部电极结构包括下部电极 阻挡层和形成在下电极阻挡层上的下金属电极，以及上装置，包括上基板，形成在上基板下的上绝缘层和形成在上绝缘层中的上电极结构，上电极 结构包括从其下表面上的上绝缘层的内部延伸的上电极阻挡层和形成在上电极阻挡层上的上金属电极。 下部金属电极与上部金属电极直接接触。