公开(公告)号：US20190148374A1

公开(公告)日：2019-05-16

申请号：US16013734

申请日：2018-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DEOK-HAN BAE ,  SANG-YOUNG KIM ,  BYUNG-CHAN RYU ,  JONG-HO YOU ,  DA-UN JEON

IPC: H01L27/088 ,  H01L29/78 ,  H01L27/02 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768

Abstract: An integrated circuit device includes a substrate having a fin-type active region that extends in a first direction, a gate structure that intersects the fin-type active region on the substrate and extends in a second direction perpendicular to the first direction and parallel to an upper surface of the substrate, a guide pattern that extends on the gate structure in the second direction and has an inclined side surface that extends in the second direction, source/drain regions disposed on both sides of the gate structure, and a first contact that is electrically connected to one of the source/drain regions and in which an upper portion contacts the inclined side surface of the guide pattern. The width of an upper portion of the guide pattern in the first direction is less than the width of a lower portion of the guide pattern in the first direction.

公开(公告)号：US20160343825A1

公开(公告)日：2016-11-24

申请号：US14984037

申请日：2015-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DEOK-HAN BAE ,  KYUNG-SOO KIM ,  CHUL-SUNG KIM ,  WOO-CHEOL SHIN ,  HWl-CHAN JUN

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/45

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/823418 ,  H01L21/823437 ,  H01L23/485 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a gate electrode and a source or drain disposed at opposite sides of the gate electrode, forming an interlayer insulating layer covering the gate electrode and the source or drain, forming a contact hole exposing the source or drain in the interlayer insulating layer, forming a silicide layer on a bottom surface of the contact hole, and forming a spacer on sidewalls of the contact hole and an upper surface of the silicide layer.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括形成设置在栅电极的相对侧的栅极和源极或漏极，形成覆盖栅电极和源极或漏极的层间绝缘层，形成暴露层间绝缘层中的源极或漏极的接触孔 在接触孔的底表面上形成硅化物层，并在接触孔的侧壁和硅化物层的上表面上形成间隔物。