公开(公告)号：US20160285452A1

公开(公告)日：2016-09-29

申请号：US15178154

申请日：2016-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAL-HEE LEE ,  JAE-WOO SEO ,  MIN-HO PARK

IPC: H03K19/00 ,  G06F17/50 ,  H03K19/0185

CPC classification number: H03K19/0013 ,  G06F17/5072 ,  H03K19/018507 ,  H03K19/018521 ,  H03K19/0944

Abstract: An integrated circuit (IC) includes at least one unit cell. The at least one unit cell includes a first bit circuit configured to process a first bit signal, a second bit circuit configured to process a second bit signal, a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage, and a second well biased to a second voltage that is different from the first voltage. Each of the first and second bit circuits includes at least one transistor from among a plurality of transistors disposed in the first well.

公开(公告)号：US20240203974A1

公开(公告)日：2024-06-20

申请号：US18596731

申请日：2024-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG-HO DO ,  DAL-HEE LEE ,  JIN-YOUNG LIM ,  TAE-JOONG SONG ,  JONG-HOON JUNG

IPC: H01L27/02 ,  G06F30/00 ,  G11C5/06 ,  G11C8/16 ,  G11C11/412 ,  H01L21/768 ,  H01L27/088 ,  H01L27/118

CPC classification number: H01L27/0207 ,  G06F30/00 ,  G11C5/063 ,  G11C8/16 ,  G11C11/412 ,  H01L21/76895 ,  H01L27/088 ,  H01L27/11807 ,  H01L2027/11875

Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.

公开(公告)号：US20170093401A1

公开(公告)日：2017-03-30

申请号：US15211468

申请日：2016-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAL-HEE LEE ,  JAE-WOO SEO

IPC: H03K19/0185 ,  H03K19/00 ,  H01L27/092

CPC classification number: H03K19/018521 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0928 ,  H03K19/0013

Abstract: An integrated circuit (IC) includes a first circuit, a first well and a second circuit. The first circuit is disposed on a substrate and configured to shift a first bit signal between a first voltage logic level and a second logic voltage level. The first well is disposed in a cell on the substrate and biased to a first voltage. The first well is spaced apart from a first edge of the cell. The second well is disposed in the cell and biased to a second voltage. The second well is disposed to contact a second edge of the cell opposite to the first edge. The first circuit includes a plurality of transistors respectively disposed in the first and second wells.

公开(公告)号：US20190383875A1

公开(公告)日：2019-12-19

申请号：US16552109

申请日：2019-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HA-YOUNG KIM ,  SUNG-WEE CHO ,  DAL-HEE LEE ,  JAE-HA LEE

IPC: G01R31/3185 ,  H03K3/3562

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

公开(公告)号：US20170328954A1

公开(公告)日：2017-11-16

申请号：US15663852

申请日：2017-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HA-YOUNG KIM ,  SUNG-WEE CHO ,  DAL-HEE LEE ,  JAE-HA LEE

IPC: G01R31/3185 ,  H03K3/3562

CPC classification number: G01R31/318541 ,  H03K3/35625

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.