公开(公告)号：US20230207429A1

公开(公告)日：2023-06-29

申请号：US18119560

申请日：2023-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO DO ,  TAE-JOONG SONG ,  SEUNG-YOUNG LEE ,  JONG-HOON JUNG

IPC: H01L23/48 ,  H01L23/482 ,  H01L27/02 ,  H01L27/118 ,  H01L23/485 ,  H01L21/768 ,  G06F30/394

CPC classification number: H01L23/481 ,  G06F30/394 ,  H01L21/76895 ,  H01L23/482 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/11807 ,  G06F30/392 ,  H01L2027/11875

Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.

公开(公告)号：US20240203974A1

公开(公告)日：2024-06-20

申请号：US18596731

申请日：2024-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG-HO DO ,  DAL-HEE LEE ,  JIN-YOUNG LIM ,  TAE-JOONG SONG ,  JONG-HOON JUNG

IPC: H01L27/02 ,  G06F30/00 ,  G11C5/06 ,  G11C8/16 ,  G11C11/412 ,  H01L21/768 ,  H01L27/088 ,  H01L27/118

CPC classification number: H01L27/0207 ,  G06F30/00 ,  G11C5/063 ,  G11C8/16 ,  G11C11/412 ,  H01L21/76895 ,  H01L27/088 ,  H01L27/11807 ,  H01L2027/11875

Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.

公开(公告)号：US20230223319A1

公开(公告)日：2023-07-13

申请号：US18123296

申请日：2023-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO DO ,  TAE-JOONG SONG ,  SEUNG-YOUNG LEE ,  JONG-HOON JUNG

IPC: H01L23/48 ,  H01L27/02 ,  G06F30/394 ,  H01L23/482 ,  H01L23/485 ,  H01L21/768 ,  H01L27/118 ,  G06F30/392

CPC classification number: H01L23/481 ,  H01L27/0207 ,  G06F30/394 ,  H01L23/482 ,  H01L23/485 ,  H01L21/76895 ,  H01L27/11807 ,  G06F30/392 ,  H01L2027/11875

Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.

公开(公告)号：US20200334407A1

公开(公告)日：2020-10-22

申请号：US16915369

申请日：2020-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-TAE KIM ,  JUNG-HO DO ,  TAE-JOONG SONG ,  DOO-HEE CHO ,  SEUNG-YOUNG LEE

IPC: G06F30/394 ,  G06F30/392

Abstract: A method of designing an integrated circuit includes receiving input data defining the integrated circuit, receiving information from a standard cell library including a plurality of standard cells, receiving information from a modified cell library including at least one modified cell having a same function as a corresponding standard cell among the plurality of standard cells and having a higher routability than the corresponding standard cell and generating output data by performing placement and routing in response to the input data, the information from the standard cell library and the information from the modified cell library.

公开(公告)号：US20170277819A1

公开(公告)日：2017-09-28

申请号：US15351545

申请日：2016-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HA-YOUNG KIM ,  SUNG-WE CHO ,  TAE-JOONG SONG

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G03F1/14 ,  G03F7/70425 ,  G03F7/70433 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12

Abstract: A computer-implemented method of designing an integrated circuit (IC) includes allocating a plurality of colors to a plurality of patterns corresponding to one layer of a first cell so that a multi-patterning technology is designated for use in forming the plurality of patterns, the first cell being a multi-height cell corresponding to a plurality of rows, generating a plurality of shift cells, in which a color remapping operation associated with the plurality of patterns is performed for each row, with respect to the first cell, and storing a cell set including the first cell and the plurality of shift cells in a standard cell library.

公开(公告)号：US20210057310A1

公开(公告)日：2021-02-25

申请号：US17075141

申请日：2020-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO DO ,  TAE-JOONG SONG ,  SEUNG-YOUNG LEE ,  JONG-HOON JUNG

IPC: H01L23/48 ,  H01L23/482 ,  H01L27/02 ,  H01L27/118 ,  H01L23/485 ,  H01L21/768 ,  G06F30/394

Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.

公开(公告)号：US20140380256A1

公开(公告)日：2014-12-25

申请号：US14258065

申请日：2014-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAE-JOONG SONG ,  JAE-HO PARK ,  KWANG-OK JEONG

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G03F1/70 ,  G03F7/0035 ,  G06F17/5068 ,  G06F17/5077

Abstract: A double patterning layout design method comprises defining critical paths comprising a first path and a second path on a schematic circuit, and defining a double patterning layout divided into a first mask layout having a first color and a second mask layout having a second color, the double patterning layout corresponding to the schematic circuit. The defining of the double patterning layout comprises anchoring the critical paths on the schematic circuit.

Abstract translation: 双重图案化布局设计方法包括在原理图电路上定义包括第一路径和第二路径的关键路径，并且限定分成具有第一颜色的第一掩模布局和具有第二颜色的第二掩模布局的双图案布局， 双重图案布局对应于原理图电路。 双重图案化布局的定义包括将关键路径锚定在原理图电路上。

公开(公告)号：US20190252297A1

公开(公告)日：2019-08-15

申请号：US16394961

申请日：2019-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO DO ,  TAE-JOONG SONG ,  SEUNG-YOUNG LEE ,  JONG-HOON JUNG

IPC: H01L23/48 ,  G06F17/50 ,  H01L23/482 ,  H01L27/02 ,  H01L27/118

Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.

公开(公告)号：US20180226323A1

公开(公告)日：2018-08-09

申请号：US15865941

申请日：2018-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO DO ,  TAE-JOONG SONG ,  SEUNG-YOUNG LEE ,  JONG-HOON JUNG

IPC: H01L23/48 ,  G06F17/50 ,  H01L23/482

CPC classification number: H01L23/481 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/482 ,  H01L27/0207

Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.

公开(公告)号：US20150221644A1

公开(公告)日：2015-08-06

申请号：US14488628

申请日：2014-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KANG-HYUN BAEK ,  JIN-HYUN NOH ,  TAE-JOONG SONG ,  GI-YOUNG YANG ,  SANG-KYU OH

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/417 ,  G06F17/50

CPC classification number: H01L27/0886 ,  G06F17/5068 ,  H01L27/1104 ,  H01L29/785 ,  H01L29/7851

Abstract: A layout design system for designing a semiconductor device includes a processor, a storage module storing an intermediate design, and a correction module used by the processor to correct the intermediate design. The intermediate design includes an active region and dummy designs on the active region. Each dummy design includes a dummy structure and dummy spacers disposed at opposite sides of the dummy structure. The correction module is configured to alter widths of regions of at least some of the dummy designs. The corrected design is used to produce a semiconductor device having an active fin, a hard mask layer disposed on the active fin, a gate structure crossing the over the hard mask layer, and a spacer disposed on at least one side of the gate structure. The hard mask layer, and the active fin, are provided with widths that vary due to the dummy designs.

Abstract translation: 用于设计半导体器件的布局设计系统包括处理器，存储中间设计的存储模块和由处理器用于校正中间设计的校正模块。 中间设计包括有源区域和有源区域的虚拟设计。 每个虚拟设计包括虚拟结构和设置在虚拟结构的相对侧的虚设间隔物。 校正模块被配置为改变至少一些虚拟设计的区域的宽度。 校正后的设计用于制造具有活性鳍片，设置在活性鳍片上的硬掩模层，与硬掩模层之间交叉的栅极结构以及设置在栅极结构的至少一侧上的间隔物的半导体器件。 硬掩模层和活动翅片具有由于虚拟设计而变化的宽度。