公开(公告)号：US06882031B2

公开(公告)日：2005-04-19

申请号：US10012665

申请日：2001-10-30

Applicant: Ronald A. Weimer ,  Fernando Gonzalez

Inventor： Ronald A. Weimer ,  Fernando Gonzalez

IPC: H01L21/28 ,  H01L21/30 ,  H01L21/318 ,  H01L23/31 ,  H01L29/51 ,  H01L29/06 ,  H01L29/94

CPC classification number: H01L21/28185 ,  H01L21/0217 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/3003 ,  H01L21/3185 ,  H01L23/3171 ,  H01L29/513 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

Abstract: A passivation method includes disassociating ammonia so as to expose at least interfaces between silicon-containing and passivation structures to at least hydrogen species derived from the ammonia and forming an encapsulant layer that is positioned so as to substantially contain the hydrogen species in the presence of the interfaces. The hydrogen passivation reduces a concentration of dangling silicon bonds at the interfaces by as much as about two orders of magnitude or greater. The encapsulant layer, which may include silicon nitride, prevents hydrogen species from escaping therethrough as high temperature processes are subsequently conducted. Once high temperature processes have been completed, portions of the encapsulant layer may be removed, as needed, to provide access to features of the semiconductor device structure that underlie the encapsulant layer. Semiconductor device structures that have been passivated in such a manner are also disclosed.

Abstract translation: 钝化方法包括使氨分解，以至少将含硅和钝化结构之间的界面暴露于源自氨的至少氢物质，并形成一个密封剂层，该密封剂层被定位成在存在下基本上含有氢物质 接口 氢钝化将界面处的悬挂硅键的浓度降低了大约两个数量级或更多。 可以包括氮化硅的密封剂层通过随后进行高温处理来防止氢物质逸出。 一旦高温处理已经完成，根据需要可以去除部分密封剂层，以提供对构成密封剂层的半导体器件结构的特征的访问。 已经以这种方式钝化的半导体器件结构也被公开。

公开(公告)号：US06908868B2

公开(公告)日：2005-06-21

申请号：US10377495

申请日：2003-02-27

Applicant: Ronald A. Weimer ,  Fernando Gonzalez

Inventor： Ronald A. Weimer ,  Fernando Gonzalez

IPC: H01L21/28 ,  H01L21/30 ,  H01L21/318 ,  H01L23/31 ,  H01L29/51 ,  H01L21/26

CPC classification number: H01L21/28185 ,  H01L21/0217 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/3003 ,  H01L21/3185 ,  H01L23/3171 ,  H01L29/513 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

Abstract: A method for passivating at least interfaces between structures formed from a conductive or semiconductive material and adjacent dielectric structures so as to reduce a concentration of dangling silicon bonds at these interfaces and to reduce or eliminate the occurrence of unwanted voltage changes across the dielectric structures. The method includes exposing at least the interfaces to at least hydrogen species and forming an encapsulant layer that substantially contains the hydrogen species in the presence of the interfaces. The encapsulant layer substantially prevents the hydrogen species from escaping therethrough as processes that require temperatures of at least about 400° C. or of at least about 600° C. are conducted. Once such high temperature processes have been completed, portions of the encapsulant layer may be removed. Methods and systems for passivating semiconductor device structures are also disclosed, as are semiconductor device structures passivated according to the disclosed methods.

Abstract translation: 一种用于钝化由导电或半导体材料和相邻电介质结构形成的结构之间的至少界面的方法，以便减少在这些界面处的悬挂硅键的浓度，并且减少或消除跨介电结构的不期望的电压变化的发生。 该方法包括至少将界面暴露于至少氢物质并形成在界面存在下基本上含有氢物质的密封剂层。 当需要至少约400℃或至少约600℃的温度的工艺时，密封剂层基本上防止氢物质逸出。 一旦这样的高温过程完成，可以去除部分密封剂层。 还公开了钝化半导体器件结构的方法和系统，半导体器件结构根据所公开的方法钝化。

公开(公告)号：US06544908B1

公开(公告)日：2003-04-08

申请号：US09650784

申请日：2000-08-30

Applicant: Ronald A. Weimer ,  Fernando Gonzalez

Inventor： Ronald A. Weimer ,  Fernando Gonzalez

IPC: H01L2126

CPC classification number: H01L21/28185 ,  H01L21/0217 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/3003 ,  H01L21/3185 ,  H01L23/3171 ,  H01L29/513 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

Abstract: A method for passivating at least interfaces between structures formed from a material including silicon and adjacent dielectric structures so as to reduce a concentration of dangling silicon bonds at these interfaces and to reduce or eliminate the occurrence of unwanted voltage changes across the dielectric structures. The method includes disassociating ammonia so as to expose at least the interfaces to at least hydrogen species derived from the ammonia and forming an encapsulant layer that is positioned so as to substantially contain the hydrogen species in the presence of the interfaces. The hydrogen-passivation reduces a concentration of dangling silicon bonds at the interfaces by as much as about two orders of magnitude or greater. The encapsulant layer, which may include a silicon nitride, substantially prevents the hydrogen species from escaping therethrough as processes that require temperatures of at least about 400° C. or of at least about 600° C. are conducted. Once such high temperature processes have been completed, portions of the encapsulant layer may be removed, as needed, to provide access to features of the semiconductor device structure that underlie the encapsulant layer. Methods and systems for passivating semiconductor device structures are also disclosed, as are semiconductor device structures that have been passivated in accordance with the disclosed methods.

Abstract translation: 一种用于钝化由包括硅和相邻电介质结构的材料形成的结构之间的至少界面的方法，以便减少在这些界面处的悬挂硅键的浓度，并且减少或消除跨介电结构的不期望的电压变化的发生。 该方法包括使氨分解，以至少将界面暴露于至少衍生自氨的氢物质，并形成在界面存在下基本上含有氢物质的密封剂层。 氢钝化将界面处的悬挂硅键的浓度降低了大约两个数量级或更多。 可以包括氮化硅的密封剂层基本上防止氢物质从其中逸出，因为进行需要至少约400℃或至少约600℃的温度的工艺。 一旦完成了这样的高温处理，就可以根据需要去除部分密封剂层，以提供对作为密封剂层的基础的半导体器件结构的特征的访问。 还公开了用于钝化半导体器件结构的方法和系统，以及已经根据所公开的方法钝化的半导体器件结构。

公开(公告)号：US09082714B2

公开(公告)日：2015-07-14

申请号：US13993444

申请日：2011-09-22

Applicant: Randy J. Koval ,  Max F. Hineman ,  Ronald A. Weimer ,  Vinayak K. Shamanna ,  Thomas M. Graettinger ,  William R. Kueber ,  Christopher Larsen ,  Alex J. Schrinsky

Inventor： Randy J. Koval ,  Max F. Hineman ,  Ronald A. Weimer ,  Vinayak K. Shamanna ,  Thomas M. Graettinger ,  William R. Kueber ,  Christopher Larsen ,  Alex J. Schrinsky

IPC: H01L21/76 ,  H01L21/306 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L21/30604 ,  H01L21/76 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: Embodiments of the present disclosure are directed towards use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及使用蚀刻处理后字幕定义来改善闪存器件中的数据保持。 在一个实施例中，一种方法包括在衬底上形成多个字线结构，其中多个字线结构中的各个字线结构包括具有导电材料的控制栅极和在控制栅极上形成有电绝缘材料的盖， 沉积电绝缘材料以在单个字线结构的表面上形成衬垫，以及蚀刻衬垫以去除衬垫的至少一部分。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20090097320A1

公开(公告)日：2009-04-16

申请号：US11871339

申请日：2007-10-12

Applicant: Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D. V. Ramaswamy ,  Ronald A. Weimer ,  Arup Bhattacharyya

Inventor： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D. V. Ramaswamy ,  Ronald A. Weimer ,  Arup Bhattacharyya

IPC: G11C16/04 ,  H01L29/792

CPC classification number: G11C16/0483 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0475 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  Y10S977/943

Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

Abstract translation: 一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。 电介质材料可以包括高k材料。 一个或多个电荷捕获区可以包括金属材料。 这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。 一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。 一些实施例包括包括存储器单元的电子系统。 一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

公开(公告)号：US07489000B2

公开(公告)日：2009-02-10

申请号：US11358647

申请日：2006-02-21

Applicant: Ronald A. Weimer

Inventor： Ronald A. Weimer

IPC: H01L29/94

CPC classification number: H01L21/02332 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02183 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/0805 ,  H01L28/56 ,  H01L28/84

Abstract: Methods for fuming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon. The nitridized oxynitride layer inhibits oxidation of the underlying polysilicon layer in a post-treatment oxidizing anneal of the high K dielectric, thus maintaining the oxide layer as a thin layer over the polysilicon layer.

Abstract translation: 提供了在多晶硅衬底上形成电介质层的方法，其用于构建电容器和其它半导体电路部件。 利用多晶硅层（例如HSG多晶硅电容器电极）在小于800℃下的自限制性一氧化氮（NO）退火，以在多晶硅上生长约40埃或更少的薄氧化物（氧氮化物）层 层。 NO退火在多晶硅 - 氧化物界面处提供氮层，限制多晶硅层的进一步氧化和氧化物层的生长。 将氧化物层暴露于含氮气体中以氮化氧化物层的表面并降低氧化物层的有效介电常数。 该方法特别适用于在多晶硅上形成高K电介质绝缘层，例如五氧化二钽。 氮化氮氧化物层在高K电介质的后处理氧化退火中抑制下面的多晶硅层的氧化，从而将氧化物层保持在多晶硅层上的薄层。

公开(公告)号：US07344755B2

公开(公告)日：2008-03-18

申请号：US10646673

申请日：2003-08-21

Applicant: Kevin L. Beaman ,  Ronald A. Weimer ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Trung T. Doan ,  Cem Basceri ,  David J. Kubista ,  Lingyi A. Zheng

Inventor： Kevin L. Beaman ,  Ronald A. Weimer ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Trung T. Doan ,  Cem Basceri ,  David J. Kubista ,  Lingyi A. Zheng

IPC: C23C16/00

CPC classification number: C23C16/45546 ,  C23C16/4404

Abstract: The present disclosure provides methods and apparatus that may be used to process microfeature workpieces, e.g., semiconductor wafers. Some aspects have particular utility in depositing TiN in a batch process. One implementation involves pretreating a surface of a process chamber by contemporaneously introducing first and second pretreatment precursors (e.g., TiCl4 and NH3) to deposit a pretreatment material on a the chamber surface. After the pretreatment, the first microfeature workpiece may be placed in the chamber and TiN may be deposited on the microfeature workpiece by alternately introducing quantities of first and second deposition precursors.

Abstract translation: 本公开提供了可用于处理微特征工件（例如半导体晶片）的方法和装置。 一些方面在分批过程中沉积TiN具有特殊的用途。 一个实施方案包括通过同时引入第一和第二预处理前体（例如，TiCl 4和NH 3）来预处理处理室的表面，以将预处理材料沉积在室表面上 。 在预处理之后，可以将第一微特征工件放置在腔室中，并且可以通过交替地引入量的第一和第二沉积前体将TiN沉积在微特征工件上。

公开(公告)号：US07235138B2

公开(公告)日：2007-06-26

申请号：US10646607

申请日：2003-08-21

Applicant: Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Ronald A. Weimer ,  David J. Kubista ,  Kevin L. Beaman ,  Cem Basceri

Inventor： Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Ronald A. Weimer ,  David J. Kubista ,  Kevin L. Beaman ,  Cem Basceri

IPC: C23C16/00 ,  H01L21/306 ,  C23F1/00

CPC classification number: C23C16/4583 ,  C23C16/45546 ,  C23C16/45578 ,  Y10S206/832

Abstract: The present disclosure describes apparatus and methods for processing microfeature workpieces, e.g., by depositing material on a microelectronic semiconductor using atomic layer deposition. Some of these apparatus include microfeature workpiece holders that include gas distributors. One exemplary implementation provides a microfeature workpiece holder adapted to hold a plurality of microfeature workpieces. This workpiece holder includes a plurality of workpiece supports and a gas distributor. The workpiece supports are adapted to support a plurality of microfeature workpieces in a spaced-apart relationship to define a process space adjacent a surface of each microfeature workpiece. The gas distributor includes an inlet and a plurality of outlets, with each of the outlets positioned to direct a flow of process gas into one of the process spaces.

Abstract translation: 本公开描述了用于处理微特征工件的装置和方法，例如通过使用原子层沉积在微电子半导体上沉积材料。 这些设备中的一些包括微型工件保持器，其包括气体分配器。 一个示例性实施例提供了适于保持多个微特征工件的微特征工件保持器。 该工件保持器包括多个工件支撑件和气体分配器。 工件支撑件适于以间隔的关系支撑多个微特征工件以限定与每个微特征工件的表面相邻的工艺空间。 气体分配器包括入口和多个出口，其中每个出口被定位成将处理气体流引导到处理空间中的一个中。

公开(公告)号：US07084448B2

公开(公告)日：2006-08-01

申请号：US10786348

申请日：2004-02-24

Applicant: Scott J. DeBoer ,  Ronald A. Weimer ,  John T. Moore

Inventor： Scott J. DeBoer ,  Ronald A. Weimer ,  John T. Moore

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10888 ,  H01L21/76831 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91 ,  H01L29/41725

Abstract: A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose the digit line plug contact pads, and a liner is provided in the opening. A portion of the digit line plug is formed, then the dielectric layer is etched again to expose the capacitor storage cell contact pads. A capacitor bottom plate is formed to contact the storage cell contact pads, then the dielectric layer is etched a third time using the liner and the bottom plate as an etch stop layer. A capacitor cell dielectric layer and capacitor top plate are formed which provide a double-sided container cell. An additional dielectric layer is formed, then the additional dielectric layer, cell top plate, and the cell dielectric are etched to expose the digit line plug portion. Finally, a second digit line plug portion is formed to contact the first plug portion. A novel structure resulting from the inventive method is also discussed.

Abstract translation: 在形成半导体器件期间使用的方法包括提供晶片衬底组件，其包括接触半导体晶片的多个数字线插头接触焊盘和电容器存储单元接触焊盘。 电介质层设置在晶片衬底组件上并被蚀刻以暴露数字线插头接触垫，并且衬套设置在开口中。 形成数字线插头的一部分，然后再次蚀刻电介质层以暴露电容器存储单元接触垫。 电容器底板形成为与存储单元接触焊盘接触，然后使用衬垫和底板作为蚀刻停止层，第三次蚀刻电介质层。 形成电容器单元电介质层和电容器顶板，其提供双面容器单元。 形成附加的电介质层，然后蚀刻附加的电介质层，电池顶板和电池电介质以露出数字线插头部分。 最后，形成第二数字线插头部分以接触第一插头部分。 还讨论了由本发明方法产生的新颖结构。

公开(公告)号：US07056806B2

公开(公告)日：2006-06-06

申请号：US10665099

申请日：2003-09-17

Applicant: Cem Basceri ,  Trung T. Doan ,  Ronald A. Weimer ,  Kevin L. Beaman ,  Lyle D. Breiner ,  Lingyi A. Zheng ,  Er-Xuan Ping ,  Demetrius Sarigiannis ,  David J. Kubista

Inventor： Cem Basceri ,  Trung T. Doan ,  Ronald A. Weimer ,  Kevin L. Beaman ,  Lyle D. Breiner ,  Lingyi A. Zheng ,  Er-Xuan Ping ,  Demetrius Sarigiannis ,  David J. Kubista

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/36 ,  H01L21/04 ,  H01L21/261

CPC classification number: C23C16/45527 ,  C23C16/34 ,  C23C16/45546

Abstract: The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.