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公开(公告)号：US6002881A
公开(公告)日：1999-12-14
申请号：US932053
申请日：1997-09-17
CPC分类号： G06F9/3552 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/325 , G06F9/355 , G06F9/384 , G06F9/3877 , G06F9/3879
摘要： A digital signal processing system comprising a central processing unit core 2, a memory 8 and a coprocessor 4 operates using coprocessor memory access instructions (e.g. LDC, STC). The addressing mode information within these coprocessor memory access instructions (P, U, W, Offset) not only controls the addressing mode used by the central processing unit core 2 but is also used by the coprocessor 4 to determine the number of data words in the transfer being specified such that the coprocessor 4 can terminate the transfer at the appropriate time. Knowledge in advance of the number of words in a transfer is also advantageous in some bus systems, such as those that can be used with synchronous DRAM. The Offset field within the instruction may be used to specify changes to be made in the value provided by the central processing unit core 2 upon execution of a particular instruction and also to specify the number of words in the transfer. This arrangement is well suited to working through a regular array of data such as in digital signal processing operations. If the Offset field is not being used, then the number of words to be transferred may default to 1.
摘要翻译： 包括中央处理单元核心2，存储器8和协处理器4的数字信号处理系统使用协处理器存储器访问指令（例如LDC，STC）进行操作。 这些协处理器存储器访问指令（P，U，W，偏移）内的寻址模式信息不仅控制中央处理单元核心2所使用的寻址模式，而且还由协处理器4使用来确定数据字的数量 传输被指定为使得协处理器4可以在适当的时间终止转移。 在一些总线系统中，诸如可以与同步DRAM一起使用的那些总线系统中的转移数量之前的知识也是有利的。 指令内的偏移字段可以用于指定在执行特定指令时由中央处理单元核心2提供的值进行改变，并且还指定转移中的字数。 这种布置非常适合通过数字信号处理操作中的常规数据阵列进行工作。 如果未使用偏移字段，则要传输的字数可能默认为1。
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公开(公告)号：US06999985B2
公开(公告)日：2006-02-14
申请号：US09941790
申请日：2001-08-30
IPC分类号： G06F7/38
CPC分类号： G06F7/505 , G06F7/49931 , G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F2207/3828
摘要： A data processing system is provided with an instruction (ADD8TO16) that unpacks non-adjacent portions of a data word using sign or zero extension and combines this with a single-instruction-multiple-data type arithmetic operation, such as an add, performed in response to the same instruction. The instruction is well suited to use within systems having a data path (2) including a shifting circuit (6) upstream of an arithmetic circuit (8).
摘要翻译： 数据处理系统提供有使用符号或零扩展来解开数据字的非相邻部分的指令（ADD8TO16），并将其与单指令多数据类型算术运算（例如，在 对同一指令的回应。 该指令非常适合于在具有在运算电路（8）上游的移位电路（6）的数据路径（2）的系统内使用。
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3.发明授权Data processing apparatus and method for moving data between registers and memory in response to an access instruction having an alignment specifier identifying an alignment to be associated with a start address 有权数据处理装置和方法，用于响应于具有标识与开始地址相关联的对准的对准指定符的访问指令来在寄存器和存储器之间移动数据公开(公告)号：US07210023B2
公开(公告)日：2007-04-24
申请号：US10889470
申请日：2004-07-13
IPC分类号： G06F7/00
CPC分类号： G06F9/3004 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30116 , G06F9/30138 , G06F9/30181 , G06F9/3816
摘要： The present invention provides a data processing apparatus and method for performing aligned access operations. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements, and a processor operable to perform a data processing operation on one or more data elements accessed in at least one of the registers. Further, access logic is provided which is operable in response to an access instruction to perform an access operation in order to move a number of data elements between specified registers and a portion of a memory, the portion having a start address specified by the access instruction. Further, the access instruction has an alignment specifier associated therewith which is settable either to a first value or one of a plurality of second values. The first value indicates that the start address is to be treated as byte aligned, and each of the second values indicates a different predetermined alignment that the start address is to be treated as conforming to. The access logic is then operable to adapt the access operation in dependence on the value of alignment specifier. This provides significantly improved flexibility in the performance of access operations.
摘要翻译： 本发明提供一种用于执行对准访问操作的数据处理装置和方法。 数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器，以及可操作以对在至少一个寄存器中访问的一个或多个数据元素执行数据处理操作的处理器。 此外，提供访问逻辑，其可响应于访问指令而操作以执行访问操作，以便在指定的寄存器和存储器的一部分之间移动多个数据元素，该部分具有由访问指令指定的起始地址 。 此外，访问指令具有与其相关联的对齐说明符，其可设置为第一值或多个第二值中的一个。 第一个值表示起始地址被视为字节对齐，并且每个第二个值指示起始地址被视为符合的不同的预定对齐方式。 然后，访问逻辑可操作以根据对准说明符的值来适应访问操作。 这样可以显着提高访问操作性能的灵活性。
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公开(公告)号：US06598061B1
公开(公告)日：2003-07-22
申请号：US09594081
申请日：2000-06-15
IPC分类号： G06F772
CPC分类号： G06F7/728
摘要： The present invention provides a system, method and computer program for performing a modular multiplication a*b*2−N modulo n, where a, b and n are N-bit integers. The system comprises a multiplier for multiplying a Y-bit number by a Z-bit number, and partitioning logic for partitioning the integer a into a plurality of first sections, each first section being of a size which is a multiple of Y, and for partitioning the integer b into a plurality of second sections, each second section being of a size which is a multiple of Z. A multiplication unit is then provided to apply operations to control the multiplier to perform a sequence of multiplications to multiply one of said first sections by one of said second sections in order to generate a number of output operands for use in subsequent operations performed by the multiplication unit. A controller is used to sequentially input one of said first sections and one of said second sections into the multiplication unit along with predetermined ones of said output operands from preceding operations performed by the multiplication unit, until each first section has been multiplied by each second section. By this approach, a multiplication unit can be provided which is of a fixed size, irrespective of the size of the input integers, a b and n. This alleviates the requirements for increasingly larger fast storage, the size of the fast storage being dependent not on the ultimate size of the N-bit integers, but rather on the predetermined size of the sections into which those integers are partitioned.
摘要翻译： 本发明提供了一种用于执行乘法a * b * 2-N模n的系统，方法和计算机程序，其中a，b和n是N位整数。 该系统包括用于将Y比特数乘以Z比特数的乘法器和用于将整数a分割成多个第一部分的分割逻辑，每个第一部分的大小是Y的倍数，并且对于 将整数b分割成多个第二部分，每个第二部分的尺寸是Z的倍数。然后提供乘法单元以施加操作以控制乘数以执行乘法序列，以乘以所述第一 以产生用于由乘法单元执行的后续操作中的多个输出操作数。 控制器用于将所述第一部分中的一个和所述第二部分中的一个顺序输入到乘法单元中，以及由乘法单元执行的先前操作的所述输出操作数中的预定的一个，直到每个第一部分已经被每个第二部分 。 通过该方法，可以提供具有固定大小的乘法单元，而与输入整数a b和n的大小无关。 这减轻了越来越大的快速存储的要求，快速存储的大小不取决于N位整数的最终大小，而是取决于这些整数被分割成的区段的预定大小。
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5.发明授权公开(公告)号：US09557994B2
公开(公告)日：2017-01-31
申请号：US12588412
申请日：2009-10-14
CPC分类号： G06F9/30021 , G06F7/4812 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/30138 , G06F9/3016 , G06F9/30167 , G06F9/30189 , G06F9/345 , G06F9/382 , G06F9/3832 , G06F9/3873 , G06F9/3887 , G06F2207/3828
摘要： A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements. An instruction decoder is responsive to at least one but no more than N rearrangement instructions, where N is an odd plural number, to generate control signals to control the processing circuitry to perform a rearrangement process at least equivalent to: obtaining as source data elements the data elements stored in N registers of said register data store as identified by the at least one re-arrangement instruction; performing a rearrangement operation to rearrange the source data elements between a regular N-way interleaved order and a de-interleaved order in order to produce a sequence of result data elements; and outputting the sequence of result data elements for storing in the register data store. This provides a particularly efficient technique for performing N-way interleave and de-interleave operations, where N is an odd number, resulting in high performance, low energy consumption, and reduced register use when compared with known prior art techniques.
摘要翻译： 提供了一种执行重排操作的数据处理装置和方法。 数据处理装置具有具有多个寄存器的寄存器数据存储器，每个寄存器存储多个数据元素。 处理电路响应于控制信号来对数据元素执行处理操作。 指令解码器响应于至少一个但不超过N个重排指令，其中N是奇数复数，以产生控制信号，以控制处理电路执行至少等同于：作为源数据元素的重新排列过程 存储在由所述至少一个重新布置指令识别的所述寄存器数据存储器的N个寄存器中的数据元素; 执行重排操作以在常规N路交错顺序和解交织顺序之间重新排列源数据元素，以便产生结果数据元素的序列; 并输出用于存储在寄存器数据存储器中的结果数据元素的序列。 这提供了一种特别有效的技术，用于执行N路交错和解交织操作，其中N是奇数，导致高性能，低能量消耗和降低的寄存器使用，与已知的现有技术相比。
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公开(公告)号：US08595280B2
公开(公告)日：2013-11-26
申请号：US12926171
申请日：2010-10-29
申请人： Dominic Hugo Symes , Mladen Wilder , Guy Larri
发明人： Dominic Hugo Symes , Mladen Wilder , Guy Larri
IPC分类号： G06F7/38
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30072 , G06F9/30101 , G06F9/3887 , G06F9/3893
摘要： A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element. Instruction decoder circuitry is responsive to a predicated multiply-accumulate instruction specifying as input operands a first input data element, a second input data element, and a predicate value, to generate control signals to control the data processing circuitry to perform a multiply-accumulate operation by: multiplying said first input data element and said second input data element to produce a multiplication data element; if the predicate value has a first value, producing a result accumulate data element by adding the multiplication data element to an initial accumulate data element; and if the predicate value has a second value, producing the result accumulate data element by subtracting the multiplication data element from the initial accumulate data element. Such an approach provides a particularly efficient mechanism for performing complex sequences of multiply-add and multiply-subtract operations, facilitating improvements in performance, energy consumption and code density when compared with known prior art techniques.
摘要翻译： 提供了一种用于执行多重累加操作的数据处理装置和方法。 数据处理装置包括响应于控制信号的数据处理电路，以对至少一个输入数据元素执行数据处理操作。 指令解码器电路响应于指定作为输入操作数的第一输入数据元素，第二输入数据元素和谓词值的预测乘法累加指令，以产生控制信号以控制数据处理电路执行乘法累加操作 通过：将所述第一输入数据元素和所述第二输入数据元素相乘以产生乘法数据元素; 如果谓词值具有第一值，则通过将乘数据元素添加到初始累加数据元素来产生结果累积数据元素; 并且如果谓词值具有第二值，则通过从初始累加数据元素中减去乘法数据元素来产生结果累积数据元素。 这种方法提供了一种特别有效的机制，用于执行乘法和乘法运算的复杂序列，与已知的现有技术相比，有助于提高性能，能量消耗和代码密度。
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7.发明授权Apparatus and method for performing rearrangement and arithmetic operations on data 有权对数据执行重排和算术运算的装置和方法公开(公告)号：US08255446B2
公开(公告)日：2012-08-28
申请号：US11987323
申请日：2007-11-29
IPC分类号： G06F7/38
CPC分类号： G06F7/768 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3885 , G06F9/3887
摘要： An apparatus and method are provided for performing rearrangement operations and arithmetic operations on data. The data processing apparatus has processing circuitry for performing Single Instruction Multiple Data (SIMD) processing operations and scalar processing operations, a register bank for storing data and control circuitry responsive to program instructions to control the processing circuitry to perform data processing operations. The control circuitry is arranged to responsive to a combined rearrangement arithmetic instruction to control the processing circuitry to perform a rearrangement operation and at least one SIMD arithmetic operation on a plurality of data elements stored in the register bank. The rearrangement operation is configurable by a size parameter derived at least in part from the register bank. The size parameter provides an indication of a number of data elements forming a rearrangement element for the purposes of the rearrangement operation. The associated method involves controlling processing circuitry to perform a rearrangement operation and at least one SIMD arithmetic operation in response to a combined rearrangement arithmetic instruction and providing the scalar logic size parameter to configure the rearrangement operation. A computer program product is also provided comprising at least one combined rearrangement arithmetic instruction.
摘要翻译： 提供了一种用于对数据执行重新排列操作和算术运算的装置和方法。 数据处理装置具有用于执行单指令多数据（SIMD）处理操作和标量处理操作的处理电路，响应于程序指令来存储数据和控制电路的寄存器组，以控制处理电路执行数据处理操作。 控制电路被布置为响应于组合重排算术指令来控制处理电路对存储在寄存器组中的多个数据元素执行重新排列操作和至少一个SIMD算术运算。 重新布置操作可以由至少部分地从寄存器库导出的尺寸参数来配置。 尺寸参数提供形成用于重排操作的重新排列元件的数量元素的数量的指示。 相关联的方法涉及控制处理电路以响应于组合重排算术指令执行重排操作和至少一个SIMD算术运算，并提供标量逻辑大小参数以配置重新排列操作。 还提供了包括至少一个组合重排算术指令的计算机程序产品。
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公开(公告)号：US20120133533A1
公开(公告)日：2012-05-31
申请号：US12926601
申请日：2010-11-29
IPC分类号： H03M7/00
CPC分类号： H03M7/4018
摘要： Arithmetic coding utilises probability values associated with contexts and context indexed values. The probability values are stored within a random access memory 6 from where they are fetched to a cache memory 8 before being supplied to an arithmetic encoder and decoder 4. The context indexed values used are mapped to the plurality of contexts employed such that context indexed values used to process data values close by in a position within the stream of data values being processed have a greater statistical likelihood of sharing a group of contexts than context values used to process data values far away in position within the stream of data values. Thus, a group of contexts for which the probability values are fetched together into the cache memory 8 will have an increased statistical likelihood of being used together in close proximity in processing the stream of data values. This reduces the number of cache flush operations and cache line fill operations.
摘要翻译： 算术编码利用与上下文和上下文索引值相关联的概率值。 概率值被存储在随机存取存储器6中，从它们被提取到高速缓冲存储器8之前被提供给算术编码器和解码器4.所使用的上下文索引值被映射到所使用的多个上下文，使得上下文索引值 用于处理在被处理的数据值的流中的位置附近的数据值具有与用于处理在数据值流内远离位置的数据值的上下文值共享一组上下文的更大的统计学可能性。 因此，将概率值一起提取到高速缓存存储器8中的一组上下文将具有在处理数据值流时紧密一起使用的增加的统计似然性。 这减少了高速缓存刷新操作和高速缓存行填充操作的数量。
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公开(公告)号：US20090187746A1
公开(公告)日：2009-07-23
申请号：US12314760
申请日：2008-12-16
申请人： Dominic Hugo Symes , Mladen Wilder
发明人： Dominic Hugo Symes , Mladen Wilder
IPC分类号： G06F9/302
CPC分类号： G06F9/30032 , G06F9/30018 , G06F9/30036
摘要： An apparatus for processing data is provided comprising processing circuitry having permutation circuitry for performing permutation operations, a register bank having a plurality of registers for storing data and control circuitry responsive to program instructions to control the processing circuitry to perform data processing operations. The control circuitry is arranged to be responsive to a control-generating instruction to generate in dependence upon a bit-mask control signals to configure permutation circuitry for performing permutation operation on an input operand. The bit-mask identifies within the input operand the first group of data elements having a first ordering and a second group of data elements having a second ordering and the permutation operation is such that it preserves one of the first ordering and the second ordering but changes the other of the first ordering and the second ordering.
摘要翻译： 提供了一种用于处理数据的装置，其包括具有用于执行置换操作的置换电路的处理电路，具有用于存储数据的多个寄存器的寄存器组和响应于程序指令控制处理电路执行数据处理操作的控制电路。 控制电路被布置为响应于控制生成指令，以根据位掩码控制信号来产生以配置用于对输入操作数执行置换操作的置换电路。 位掩码在输入操作数内识别具有第一排序的第一组数据元素和具有第二排序的第二组数据元素，并且置换操作使得其保留第一排序和第二排序之一，但是改变 第一个订购中的另一个和第二个订购。
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公开(公告)号：US07315875B2
公开(公告)日：2008-01-01
申请号：US10764473
申请日：2004-01-27
IPC分类号： G06F17/10
摘要： A method, computer program product and data processing apparatus for filtering data, in particular for use in deblocking filters. The method comprising applying a plurality of m filter coefficients which each have a value which is a negative power of two and which sum to one, to a plurality of m input data items to produce a filtered output data item, by performing a sequence of averaging calculations comprising averaging input data items to which a smallest filter coefficient is to be applied to produce first averaged data and averaging the first averaged data with other averaged input data or with input data items to which larger filter coefficients are to be applied the plurality of m filter coefficients being applied to the plurality of m input data items via a sequence of averaging calculations such that a data width of any calculated data does not exceed that of the input data being averaged.
摘要翻译： 一种用于过滤数据的方法，计算机程序产品和数据处理装置，特别是用于去块滤波器。 该方法包括：将多个m个滤波器系数应用于多个m个滤波器系数，该多个m个滤波器系数中的每一个均具有为2的负值并且与1相加的值，并通过执行平均序列来施加到多个m个输入数据项以产生滤波后的输出数据项 计算包括对要应用最小滤波器系数的输入数据项进行平均以产生第一平均数据，并且对其他平均输入数据进行平均化，或者与要对其应用更大滤波器系数的输入数据项进行平均 滤波器系数经由平均计算序列被施加到多个m个输入数据项，使得任何计算数据的数据宽度不超过正被平均的输入数据的数据宽度。
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