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公开(公告)号：US08595280B2
公开(公告)日：2013-11-26
申请号：US12926171
申请日：2010-10-29
申请人： Dominic Hugo Symes , Mladen Wilder , Guy Larri
发明人： Dominic Hugo Symes , Mladen Wilder , Guy Larri
IPC分类号： G06F7/38
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30072 , G06F9/30101 , G06F9/3887 , G06F9/3893
摘要： A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element. Instruction decoder circuitry is responsive to a predicated multiply-accumulate instruction specifying as input operands a first input data element, a second input data element, and a predicate value, to generate control signals to control the data processing circuitry to perform a multiply-accumulate operation by: multiplying said first input data element and said second input data element to produce a multiplication data element; if the predicate value has a first value, producing a result accumulate data element by adding the multiplication data element to an initial accumulate data element; and if the predicate value has a second value, producing the result accumulate data element by subtracting the multiplication data element from the initial accumulate data element. Such an approach provides a particularly efficient mechanism for performing complex sequences of multiply-add and multiply-subtract operations, facilitating improvements in performance, energy consumption and code density when compared with known prior art techniques.
摘要翻译： 提供了一种用于执行多重累加操作的数据处理装置和方法。 数据处理装置包括响应于控制信号的数据处理电路，以对至少一个输入数据元素执行数据处理操作。 指令解码器电路响应于指定作为输入操作数的第一输入数据元素，第二输入数据元素和谓词值的预测乘法累加指令，以产生控制信号以控制数据处理电路执行乘法累加操作 通过：将所述第一输入数据元素和所述第二输入数据元素相乘以产生乘法数据元素; 如果谓词值具有第一值，则通过将乘数据元素添加到初始累加数据元素来产生结果累积数据元素; 并且如果谓词值具有第二值，则通过从初始累加数据元素中减去乘法数据元素来产生结果累积数据元素。 这种方法提供了一种特别有效的机制，用于执行乘法和乘法运算的复杂序列，与已知的现有技术相比，有助于提高性能，能量消耗和代码密度。
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公开(公告)号：US20110106871A1
公开(公告)日：2011-05-05
申请号：US12926171
申请日：2010-10-29
申请人： Dominic Hugo Symes , Mladen Wilder , Guy Larri
发明人： Dominic Hugo Symes , Mladen Wilder , Guy Larri
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30072 , G06F9/30101 , G06F9/3887 , G06F9/3893
摘要： A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element. Instruction decoder circuitry is responsive to a predicated multiply-accumulate instruction specifying as input operands a first input data element, a second input data element, and a predicate value, to generate control signals to control the data processing circuitry to perform a multiply-accumulate operation by: multiplying said first input data element and said second input data element to produce a multiplication data element; if the predicate value has a first value, producing a result accumulate data element by adding the multiplication data element to an initial accumulate data element; and if the predicate value has a second value, producing the result accumulate data element by subtracting the multiplication data element from the initial accumulate data element. Such an approach provides a particularly efficient mechanism for performing complex sequences of multiply-add and multiply-subtract operations, facilitating improvements in performance, energy consumption and code density when compared with known prior art techniques.
摘要翻译： 提供了一种用于执行多重累加操作的数据处理装置和方法。 数据处理装置包括响应于控制信号的数据处理电路，以对至少一个输入数据元素执行数据处理操作。 指令解码器电路响应于指定作为输入操作数的第一输入数据元素，第二输入数据元素和谓词值的预测乘法累加指令，以产生控制信号以控制数据处理电路执行乘法累加操作 通过：将所述第一输入数据元素和所述第二输入数据元素相乘以产生乘法数据元素; 如果谓词值具有第一值，则通过将乘数据元素添加到初始累加数据元素来产生结果累积数据元素; 并且如果谓词值具有第二值，则通过从初始累加数据元素中减去乘法数据元素来产生结果累积数据元素。 这种方法提供了一种特别有效的机制，用于执行乘法和乘法运算的复杂序列，与已知的现有技术相比，有助于提高性能，能量消耗和代码密度。
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公开(公告)号：US5875465A
公开(公告)日：1999-02-23
申请号：US832091
申请日：1997-04-03
CPC分类号： G06F12/128 , G06F12/0848 , G06F12/126
摘要： A data processing system incorporating a cache memory 2 and a central processing unit. A storage control circuit 10 is responsive to a programmable partition setting PartVal to partition the cache memory between instruction words and data words in dependence upon whether the central processing unit 4 indicates with signal I/D whether the word to be stored within the cache memory 2 resulted from an instruction word cache miss or data word cache miss. The cache memory array 2 may have a programmably sized portion locked down so that it is not replaced. The selection within the complementary programmable range where overwriting takes place uses a pseudo random selection technique using pseudo random number generator in the form of a linear feedback shift register triggering incrementing of a counter.
摘要翻译： 一种包含高速缓冲存储器2和中央处理单元的数据处理系统。 存储控制电路10响应于可编程分区设置PartVal，以根据中央处理单元4是否用信号I / D指示要存储在高速缓存存储器2中的单词来指示高速缓存在指令字和数据字之间 由指令字缓存未命中或数据字高速缓存未命中引起。 缓存存储器阵列2可以具有可编程尺寸的部分锁定，使得它不被替换。 在进行重写的互补可编程范围内的选择使用伪随机数选择技术，该伪随机数生成器以线性反馈移位寄存器的形式触发递增计数器。
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公开(公告)号：US20120022862A1
公开(公告)日：2012-01-26
申请号：US13162128
申请日：2011-06-16
IPC分类号： G10L15/00
CPC分类号： G10L15/08 , G10L15/02 , G10L15/06 , G10L15/10 , G10L15/285
摘要： A speech recognition circuit comprising a circuit for providing state identifiers which identify states corresponding to nodes or groups of adjacent nodes in a lexical tree, and for providing scores corresponding to said state identifiers, the lexical tree comprising a model of words; a memory structure for receiving and storing state identifiers identified by a node identifier identifying a node or group of adjacent nodes, the memory structure being adapted to allow lookup to identify particular state identifiers, reading of the scores corresponding to the state identifiers, and writing back of the scores to the memory structure after modification of the scores; an accumulator for receiving score updates corresponding to particular state identifiers from a score update generating circuit which generates the score updates using audio input, for receiving scores from the memory structure, and for modifying the scores by adding the score updates to the scores; and a selector circuit for selecting at least one node or group of adjacent nodes of the lexical tree according to the scores.
摘要翻译： 一种语音识别电路，包括用于提供状态标识符的电路，所述状态标识符识别与词汇树中的相邻节点的节点或组相对应的状态，并且用于提供与所述状态标识符相对应的分数，所述词法树包括单词的模型; 存储器结构，用于接收和存储由识别相邻节点的节点或组的节点标识符识别的状态标识符，所述存储器结构适于允许查找以识别特定状态标识符，读取对应于状态标识符的分数，以及回写 分数修改后记忆结构的分数; 用于从得分更新生成电路接收与特定状态标识符相对应的分数更新的累加器，该分数更新生成电路使用音频输入生成分数更新，用于从存储器结构接收分数，以及通过将分数更新加到分数来修改分数; 以及选择器电路，用于根据分数来选择词汇树的至少一个相邻节点的一个或多个组。
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公开(公告)号：US5557563A
公开(公告)日：1996-09-17
申请号：US297694
申请日：1994-08-26
申请人： Guy Larri
发明人： Guy Larri
CPC分类号： G06F7/5324
摘要： An iterative multiplier having a multiplier core generating partial results upon each iteration. When an early terminate of a multiply instruction occurs, at least one of the partial results is passed to a general purpose barrel shifter for bit realignment dependent upon the number of iterations performed before the early terminate occurred. The bit realigned partial results are then passed to an arithmetic logic unit where they are added to yield the final result.
摘要翻译： 具有乘法器核心的迭代乘法器，其在每次迭代时产生部分结果。 当发生乘法指令的早期终止时，根据在提前终止发生之前执行的迭代次数，部分结果中的至少一个被传递到通用桶形移位器用于位重新对准。 然后将位重新排列的部分结果传递给算术逻辑单元，在其中添加它们以产生最终结果。
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公开(公告)号：US07979277B2
公开(公告)日：2011-07-12
申请号：US11662704
申请日：2005-09-14
IPC分类号： G10L15/00
CPC分类号： G10L15/08 , G10L15/02 , G10L15/06 , G10L15/10 , G10L15/285
摘要： A speech recognition circuit comprising a circuit for providing state identifiers which identify states corresponding to nodes or groups of adjacent nodes in a lexical tree, and for providing scores corresponding to said state identifiers, the lexical tree comprising a model of words; a memory structure for receiving and storing state identifiers identified by a node identifier identifying a node or group of adjacent nodes, said memory structure being adapted to allow lookup to identify particular state identifiers, reading of the scores corresponding to the state identifiers, and writing back of the scores to the memory structure after modification of the scores; an accumulator for receiving score updates corresponding to particular state identifiers from a score update generating circuit which generates the score updates using audio input, for receiving scores from the memory structure, and for modifying said scores by adding said score updates to said scores; and a selector circuit for selecting at least one node or group of adjacent nodes of the lexical tree according to said scores.
摘要翻译： 一种语音识别电路，包括用于提供状态标识符的电路，所述状态标识符识别与词汇树中的相邻节点的节点或组相对应的状态，并且用于提供与所述状态标识符相对应的分数，所述词法树包括单词的模型; 存储器结构，用于接收和存储由识别相邻节点的节点或组的节点标识符识别的状态标识符，所述存储器结构适于允许查找以识别特定状态标识符，读取对应于状态标识符的分数，以及回写 分数修改后记忆结构的分数; 用于从分数更新生成电路接收对应于特定状态标识符的分数更新的累加器，其使用音频输入生成分数更新，用于从所述存储器结构接收分数，以及通过将所述分数更新加到所述分数来修改所述分数; 以及选择器电路，用于根据所述分数选择词汇树的至少一个节点或相邻节点组。
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公开(公告)号：US06289417B1
公开(公告)日：2001-09-11
申请号：US09080206
申请日：1998-05-18
申请人： Guy Larri
发明人： Guy Larri
IPC分类号： G06F1208
CPC分类号： G06F9/30138 , G06F9/383
摘要： A microprocessor system comprising a register bank 6 and an execution unit 8 incorporating a barrel shifter 10 and an ALU 12 is provided. The register bank 6 has X read ports whilst at least some of the program instructions require Y input operands to be read from the register bank 6, where Y is greater than X. A cache register 18 is provided that caches previously read input operands for supply to the barrel shifter 10 and if it is detected that the same register is being read a second or subsequent time then this cached value is supplied to the barrel shifter 10 rather than requiring a further read from the register bank 6. A tag register 20 associated with each cache register 18 draws data indicating from which register within the register bank 6 the cached data value was copied. A valid flag 22 indicates that that cached data value is still current, i.e. at the corresponding register within the register bank 6 has not been overwritten.
摘要翻译： 提供一种包括寄存器组6和包括桶形移位器10和ALU12的执行单元8的微处理器系统。 寄存器组6具有X个读取端口，而至少一些程序指令要求从寄存器组6读取Y个输入操作数，其中Y大于X.提供高速缓存寄存器18，其缓存先前读取的输入操作数用于供应 到桶形移位器10，并且如果检测到正在读取相同寄存器的第二或随后的时间，则该缓存值被提供给桶形移位器10，而不需要从寄存器组6进一步读取。标签寄存器20相关联 每个缓存寄存器18绘制指示从寄存器组6中的哪个寄存器复制缓存的数据值的数据。 有效标志22指示该缓存的数据值仍然是当前的，即在寄存器组6内的相应寄存器尚未被覆盖。
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公开(公告)号：US08352262B2
公开(公告)日：2013-01-08
申请号：US13162128
申请日：2011-06-16
IPC分类号： G10L15/10
CPC分类号： G10L15/08 , G10L15/02 , G10L15/06 , G10L15/10 , G10L15/285
摘要： A speech recognition circuit comprising a circuit for providing state identifiers which identify states corresponding to nodes or groups of adjacent nodes in a lexical tree, and for providing scores corresponding to said state identifiers, the lexical tree comprising a model of words; a memory structure for receiving and storing state identifiers identified by a node identifier identifying a node or group of adjacent nodes, the memory structure being adapted to allow lookup to identify particular state identifiers, reading of the scores corresponding to the state identifiers, and writing back of the scores to the memory structure after modification of the scores; an accumulator for receiving score updates corresponding to particular state identifiers from a score update generating circuit which generates the score updates using audio input, for receiving scores from the memory structure, and for modifying the scores by adding the score updates to the scores; and a selector circuit for selecting at least one node or group of adjacent nodes of the lexical tree according to the scores.
摘要翻译： 一种语音识别电路，包括用于提供状态标识符的电路，所述状态标识符识别与词汇树中的相邻节点的节点或组相对应的状态，并且用于提供与所述状态标识符相对应的分数，所述词法树包括单词的模型; 存储器结构，用于接收和存储由识别相邻节点的节点或组的节点标识符识别的状态标识符，所述存储器结构适于允许查找以识别特定状态标识符，读取对应于状态标识符的分数，以及回写 分数修改后记忆结构的分数; 用于从得分更新生成电路接收与特定状态标识符相对应的分数更新的累加器，该分数更新生成电路使用音频输入生成分数更新，用于从存储器结构接收分数，以及通过将分数更新加到分数来修改分数; 以及选择器电路，用于根据分数来选择词汇树的至少一个相邻节点的一个或多个组。
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公开(公告)号：US20080255839A1
公开(公告)日：2008-10-16
申请号：US11662704
申请日：2005-09-14
CPC分类号： G10L15/08 , G10L15/02 , G10L15/06 , G10L15/10 , G10L15/285
摘要： A speech recognition circuit comprising a circuit for providing state identifiers which identify states corresponding to nodes or groups of adjacent nodes in a lexical tree, and for providing scores corresponding to said state identifiers, the lexical tree comprising a model of words; a memory structure for receiving and storing state identifiers identified by a node identifier identifying a node or group of adjacent nodes, said memory structure being adapted to allow lookup to identify particular state identifiers, reading of the scores corresponding to the state identifiers, and writing back of the scores to the memory structure after modification of the scores; an accumulator for receiving score updates corresponding to particular state identifiers from a score update generating circuit which generates the score updates using audio input, for receiving scores from the memory structure, and for modifying said scores by adding said score updates to said scores; and a selector circuit for selecting at least one node or group of adjacent nodes of the lexical tree according to said scores.
摘要翻译： 一种语音识别电路，包括用于提供状态标识符的电路，所述状态标识符识别与词汇树中的相邻节点的节点或组相对应的状态，并且用于提供与所述状态标识符相对应的分数，所述词法树包括单词的模型; 存储器结构，用于接收和存储由识别相邻节点的节点或组的节点标识符识别的状态标识符，所述存储器结构适于允许查找以识别特定状态标识符，读取对应于状态标识符的分数，以及回写 分数修改后记忆结构的分数; 用于从分数更新生成电路接收对应于特定状态标识符的分数更新的累加器，其使用音频输入生成分数更新，用于从所述存储器结构接收分数，以及通过将所述分数更新加到所述分数来修改所述分数; 以及选择器电路，用于根据所述分数选择词汇树的至少一个节点或相邻节点组。
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公开(公告)号：US5583804A
公开(公告)日：1996-12-10
申请号：US379014
申请日：1995-01-27
申请人： David J. Seal , Guy Larri , David V. Jaggar
发明人： David J. Seal , Guy Larri , David V. Jaggar
CPC分类号： G06F7/5443 , G06F9/30014
摘要： A data processing system is described utilizes a multiplier-accumulator 108 that performs both a first class of multiply-accumulate instructions and a second class of multiply-accumulate instructions. The first class of multiply-accumulate instructions are of the form N*N+N.fwdarw.N and the second class of multiply-accumulate instructions are of the form N*N+2N.fwdarw.2N. The second class of multiply-accumulate instructions provide a greater precision of arithmetic in a single instruction and avoid the use of excessive instruction set space by being constrained that the result is written back into the two registers from which the 2N-bit accumulate value was taken. The multiplier-accumulator also provides N*N.fwdarw.N and N*N.fwdarw.2N multiplication operations.
摘要翻译： 描述了一种数据处理系统，其利用执行第一类乘法累加指令和第二类乘法累加指令的乘法器 - 累加器108。 第一类乘法累加指令的格式为N * N + N> N，第二类乘法累加指令的格式为N * N + 2N-> 2N。 第二类乘法累加指令在单个指令中提供更高的算术精度，并避免使用过多的指令集空间来限制结果被写回到采用2N位累加值的两个寄存器中 。 乘法器累加器还提供N * N> N和N * N> 2N乘法运算。
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