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公开(公告)号：US20110106871A1
公开(公告)日：2011-05-05
申请号：US12926171
申请日：2010-10-29
申请人： Dominic Hugo Symes , Mladen Wilder , Guy Larri
发明人： Dominic Hugo Symes , Mladen Wilder , Guy Larri
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30072 , G06F9/30101 , G06F9/3887 , G06F9/3893
摘要： A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element. Instruction decoder circuitry is responsive to a predicated multiply-accumulate instruction specifying as input operands a first input data element, a second input data element, and a predicate value, to generate control signals to control the data processing circuitry to perform a multiply-accumulate operation by: multiplying said first input data element and said second input data element to produce a multiplication data element; if the predicate value has a first value, producing a result accumulate data element by adding the multiplication data element to an initial accumulate data element; and if the predicate value has a second value, producing the result accumulate data element by subtracting the multiplication data element from the initial accumulate data element. Such an approach provides a particularly efficient mechanism for performing complex sequences of multiply-add and multiply-subtract operations, facilitating improvements in performance, energy consumption and code density when compared with known prior art techniques.
摘要翻译： 提供了一种用于执行多重累加操作的数据处理装置和方法。 数据处理装置包括响应于控制信号的数据处理电路，以对至少一个输入数据元素执行数据处理操作。 指令解码器电路响应于指定作为输入操作数的第一输入数据元素，第二输入数据元素和谓词值的预测乘法累加指令，以产生控制信号以控制数据处理电路执行乘法累加操作 通过：将所述第一输入数据元素和所述第二输入数据元素相乘以产生乘法数据元素; 如果谓词值具有第一值，则通过将乘数据元素添加到初始累加数据元素来产生结果累积数据元素; 并且如果谓词值具有第二值，则通过从初始累加数据元素中减去乘法数据元素来产生结果累积数据元素。 这种方法提供了一种特别有效的机制，用于执行乘法和乘法运算的复杂序列，与已知的现有技术相比，有助于提高性能，能量消耗和代码密度。
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公开(公告)号：US08595280B2
公开(公告)日：2013-11-26
申请号：US12926171
申请日：2010-10-29
申请人： Dominic Hugo Symes , Mladen Wilder , Guy Larri
发明人： Dominic Hugo Symes , Mladen Wilder , Guy Larri
IPC分类号： G06F7/38
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30072 , G06F9/30101 , G06F9/3887 , G06F9/3893
摘要： A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element. Instruction decoder circuitry is responsive to a predicated multiply-accumulate instruction specifying as input operands a first input data element, a second input data element, and a predicate value, to generate control signals to control the data processing circuitry to perform a multiply-accumulate operation by: multiplying said first input data element and said second input data element to produce a multiplication data element; if the predicate value has a first value, producing a result accumulate data element by adding the multiplication data element to an initial accumulate data element; and if the predicate value has a second value, producing the result accumulate data element by subtracting the multiplication data element from the initial accumulate data element. Such an approach provides a particularly efficient mechanism for performing complex sequences of multiply-add and multiply-subtract operations, facilitating improvements in performance, energy consumption and code density when compared with known prior art techniques.
摘要翻译： 提供了一种用于执行多重累加操作的数据处理装置和方法。 数据处理装置包括响应于控制信号的数据处理电路，以对至少一个输入数据元素执行数据处理操作。 指令解码器电路响应于指定作为输入操作数的第一输入数据元素，第二输入数据元素和谓词值的预测乘法累加指令，以产生控制信号以控制数据处理电路执行乘法累加操作 通过：将所述第一输入数据元素和所述第二输入数据元素相乘以产生乘法数据元素; 如果谓词值具有第一值，则通过将乘数据元素添加到初始累加数据元素来产生结果累积数据元素; 并且如果谓词值具有第二值，则通过从初始累加数据元素中减去乘法数据元素来产生结果累积数据元素。 这种方法提供了一种特别有效的机制，用于执行乘法和乘法运算的复杂序列，与已知的现有技术相比，有助于提高性能，能量消耗和代码密度。
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3.发明授权Apparatus and method for performing rearrangement and arithmetic operations on data 有权对数据执行重排和算术运算的装置和方法公开(公告)号：US08255446B2
公开(公告)日：2012-08-28
申请号：US11987323
申请日：2007-11-29
IPC分类号： G06F7/38
CPC分类号： G06F7/768 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3885 , G06F9/3887
摘要： An apparatus and method are provided for performing rearrangement operations and arithmetic operations on data. The data processing apparatus has processing circuitry for performing Single Instruction Multiple Data (SIMD) processing operations and scalar processing operations, a register bank for storing data and control circuitry responsive to program instructions to control the processing circuitry to perform data processing operations. The control circuitry is arranged to responsive to a combined rearrangement arithmetic instruction to control the processing circuitry to perform a rearrangement operation and at least one SIMD arithmetic operation on a plurality of data elements stored in the register bank. The rearrangement operation is configurable by a size parameter derived at least in part from the register bank. The size parameter provides an indication of a number of data elements forming a rearrangement element for the purposes of the rearrangement operation. The associated method involves controlling processing circuitry to perform a rearrangement operation and at least one SIMD arithmetic operation in response to a combined rearrangement arithmetic instruction and providing the scalar logic size parameter to configure the rearrangement operation. A computer program product is also provided comprising at least one combined rearrangement arithmetic instruction.
摘要翻译： 提供了一种用于对数据执行重新排列操作和算术运算的装置和方法。 数据处理装置具有用于执行单指令多数据（SIMD）处理操作和标量处理操作的处理电路，响应于程序指令来存储数据和控制电路的寄存器组，以控制处理电路执行数据处理操作。 控制电路被布置为响应于组合重排算术指令来控制处理电路对存储在寄存器组中的多个数据元素执行重新排列操作和至少一个SIMD算术运算。 重新布置操作可以由至少部分地从寄存器库导出的尺寸参数来配置。 尺寸参数提供形成用于重排操作的重新排列元件的数量元素的数量的指示。 相关联的方法涉及控制处理电路以响应于组合重排算术指令执行重排操作和至少一个SIMD算术运算，并提供标量逻辑大小参数以配置重新排列操作。 还提供了包括至少一个组合重排算术指令的计算机程序产品。
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公开(公告)号：US20090187746A1
公开(公告)日：2009-07-23
申请号：US12314760
申请日：2008-12-16
申请人： Dominic Hugo Symes , Mladen Wilder
发明人： Dominic Hugo Symes , Mladen Wilder
IPC分类号： G06F9/302
CPC分类号： G06F9/30032 , G06F9/30018 , G06F9/30036
摘要： An apparatus for processing data is provided comprising processing circuitry having permutation circuitry for performing permutation operations, a register bank having a plurality of registers for storing data and control circuitry responsive to program instructions to control the processing circuitry to perform data processing operations. The control circuitry is arranged to be responsive to a control-generating instruction to generate in dependence upon a bit-mask control signals to configure permutation circuitry for performing permutation operation on an input operand. The bit-mask identifies within the input operand the first group of data elements having a first ordering and a second group of data elements having a second ordering and the permutation operation is such that it preserves one of the first ordering and the second ordering but changes the other of the first ordering and the second ordering.
摘要翻译： 提供了一种用于处理数据的装置，其包括具有用于执行置换操作的置换电路的处理电路，具有用于存储数据的多个寄存器的寄存器组和响应于程序指令控制处理电路执行数据处理操作的控制电路。 控制电路被布置为响应于控制生成指令，以根据位掩码控制信号来产生以配置用于对输入操作数执行置换操作的置换电路。 位掩码在输入操作数内识别具有第一排序的第一组数据元素和具有第二排序的第二组数据元素，并且置换操作使得其保留第一排序和第二排序之一，但是改变 第一个订购中的另一个和第二个订购。
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5.发明授权公开(公告)号：US08443170B2
公开(公告)日：2013-05-14
申请号：US12585573
申请日：2009-09-17
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30065 , G06F9/3893
摘要： An apparatus and method for performing SIMD multiply-accumulate operations includes SIMD data processing circuitry responsive to control signals to perform data processing operations in parallel on multiple data elements. Instruction decoder circuitry is coupled to the SIMD data processing circuitry and is responsive to program instructions to generate the required control signals. The instruction decoder circuitry is responsive to a single instruction (referred to herein as a repeating multiply-accumulate instruction) having as input operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicative of a plurality of iterations required, to generate control signals to control the SIMD processing circuitry. In response to those control signals, the SIMD data processing circuitry performs the plurality of iterations of a multiply-accumulate process, each iteration involving performance of N multiply-accumulate operations in parallel in order to produce N multiply-accumulate data elements. For each iteration, the SIMD data processing circuitry determines N input data elements from said first vector and a single coefficient data element from the second vector to be multiplied with each of the N input data elements. The N multiply-accumulate data elements produced in a final iteration of the multiply-accumulate process are then used to produce N multiply-accumulate results. This mechanism provides a particularly energy efficient mechanism for performing SIMD multiply-accumulate operations, as for example are required for FIR filter processes.
摘要翻译： 用于执行SIMD乘法累加操作的装置和方法包括响应于控制信号的SIMD数据处理电路，以对多个数据元素并行地执行数据处理操作。 指令解码器电路耦合到SIMD数据处理电路，并且响应于程序指令以产生所需的控制信号。 指令解码器电路响应于具有作为输入操作数的输入数据元素的第一向量，系数数据元素的第二向量和指示多个的标量值的单个指令（这里称为重复乘法累加指令） 以产生控制信号以控制SIMD处理电路。 响应于这些控制信号，SIMD数据处理电路执行多次累积处理的多次迭代，每次迭代涉及并行执行N次乘法运算，以产生N个乘法累加数据元素。 对于每次迭代，SIMD数据处理电路从所述第一向量确定N个输入数据元素，并且从第二向量确定要与N个输入数据元素中的每一个相乘的单个系数数据元素。 然后，在乘法累加过程的最终迭代中产生的N个乘法累加数据元素用于产生N个乘法累加结果。 该机制提供了用于执行SIMD乘法累加操作的特别高效的机制，例如FIR滤波器处理所需要的。
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公开(公告)号：US07895417B2
公开(公告)日：2011-02-22
申请号：US12662734
申请日：2010-04-30
CPC分类号： H03M13/4169 , G06F9/30036 , G06F9/345 , G06F9/355 , G06F9/3885 , G06F9/3887 , H04L1/0052 , H04L1/0054
摘要： A data processing system 2 is provided including an instruction decoder 34 responsive to program instructions within an instruction register 32 to generate control signals for controlling data processing circuitry 36. The instructions supported include an address calculation instruction which splits an input address value at a position dependent upon a size value into a first portion and second portion, adds a non-zero offset value to the first portion, sets the second portion to a value and then concatenates the result of the processing on the first portion and the second portion to form the output address value. Another type of instruction supported is a select-and-insert instruction. This instruction takes a first input value and shifts it by N bit positions to form a shifted value, selects N bits from within a second input value in dependence upon the first input value and then concatenates the shifted value with the N bits to form an output value. The address calculation instruction and the select-and-insert instruction described above are useful when manipulating two-dimensional data arrays, and particularly so when these are two-dimensional data arrays are formed of Viterbi trellis data through which traceback operations are to be performed.
摘要翻译： 提供数据处理系统2，其包括响应于指令寄存器32内的程序指令的指令解码器34，以产生用于控制数据处理电路36的控制信号。所支持的指令包括地址计算指令，其将位置相关的输入地址值分割 在将尺寸值分配到第一部分和第二部分中时，向第一部分添加非零偏移值，将第二部分设置为值，然后将处理结果连接在第一部分和第二部分上，以形成 输出地址值。 支持的另一种类型的指令是选择和插入指令。 该指令采用第一输入值并将其移位N位位置以形成移位值，根据第一输入值从第二输入值内选择N位，然后将移位值与N位相连以形成输出 值。 上述地址计算指令和选择和插入指令在操纵二维数据阵列时非常有用，特别是当这些二维数据阵列由维特比网格数据形成时，通过该数据将执行回溯操作。
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公开(公告)号：US07814302B2
公开(公告)日：2010-10-12
申请号：US12068903
申请日：2008-02-13
CPC分类号： H03M13/4169 , G06F9/30036 , G06F9/345 , G06F9/355 , G06F9/3885 , G06F9/3887 , H04L1/0052 , H04L1/0054
摘要： A data processing system 2 is provided including an instruction decoder 34 responsive to program instructions within an instruction register 32 to generate control signals for controlling data processing circuitry 36. The instructions supported include an address calculation instruction which splits an input address value at a position dependent upon a size value into a first portion and second portion, adds a non-zero offset value to the first portion, sets the second portion to a value and then concatenates the result of the processing on the first portion and the second portion to form the output address value. Another type of instruction supported is a select-and-insert instruction. This instruction takes a first input value and shifts it by N bit positions to form a shifted value, selects N bits from within a second input value in dependence upon the first input value and then concatenates the shifted value with the N bits to form an output value. The address calculation instruction and the select-and-insert instruction described above are useful when manipulating two-dimensional data arrays, and particularly so when these are two-dimensional data arrays are formed of Viterbi trellis data through which traceback operations are to be performed.
摘要翻译： 提供数据处理系统2，其包括响应于指令寄存器32内的程序指令的指令解码器34，以产生用于控制数据处理电路36的控制信号。所支持的指令包括地址计算指令，其将位置相关的输入地址值分割 在将尺寸值分配到第一部分和第二部分中时，向第一部分添加非零偏移值，将第二部分设置为值，然后将处理结果连接在第一部分和第二部分上，以形成 输出地址值。 支持的另一种类型的指令是选择和插入指令。 该指令采用第一输入值并将其移位N位位置以形成移位值，根据第一输入值从第二输入值内选择N位，然后将移位值与N位相连以形成输出 值。 上述地址计算指令和选择和插入指令在操纵二维数据阵列时非常有用，特别是当这些二维数据阵列由维特比网格数据形成时，通过该数据将执行回溯操作。
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8.发明申请Apparatus and method for performing magnitude detection of arthimetic operations 审中-公开用于进行拟合运算的幅度检测的装置和方法公开(公告)号：US20090112955A1
公开(公告)日：2009-04-30
申请号：US12230831
申请日：2008-09-05
IPC分类号： G06F7/00
CPC分类号： G06F9/30014 , G06F9/30036
摘要： An apparatus and method is provided comprising processing circuitry, one or more registers and control circuitry. The control circuitry is configured such that it is responsive to a combined magnitude-detecting arithmetic instruction to control the processing circuitry to perform an arithmetic operation on at least one data element and further to perform a magnitude-detecting operation. The magnitude-detecting operation calculates a magnitude-indicating result providing an indication of a position of a most-significant bit of a magnitude of a result of the arithmetic operation irrespective of whether the most-significant bit position exceeds the data element width of the at least one data element.
摘要翻译： 提供了包括处理电路，一个或多个寄存器和控制电路的装置和方法。 控制电路被配置为使得其响应于组合的幅度检测算术指令以控制处理电路对至少一个数据元执行算术运算，并进一步执行幅度检测操作。 幅度检测操作计算提供算术运算结果的大小的最高有效位的位置的指示的幅度指示结果，而不管最高有效位位置是否超过at的数据元素宽度 至少一个数据元素。
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9.发明授权Apparatus and method for performing permutation operations in which the ordering of one of a first group and a second group of data elements is preserved and the ordering of the other group of data elements is changed 有权用于执行置换操作的装置和方法，其中保留第一组和第二组数据元素中的一个的顺序，并且另一组数据元素的顺序改变公开(公告)号：US08423752B2
公开(公告)日：2013-04-16
申请号：US12314760
申请日：2008-12-16
申请人： Dominic Hugo Symes , Mladen Wilder
发明人： Dominic Hugo Symes , Mladen Wilder
CPC分类号： G06F9/30032 , G06F9/30018 , G06F9/30036
摘要： An apparatus for processing data is provided comprising processing circuitry having permutation circuitry for performing permutation operations, a register bank having a plurality of registers for storing data and control circuitry responsive to program instructions to control the processing circuitry to perform data processing operations. The control circuitry is arranged to be responsive to a control-generating instruction to generate in dependence upon a bit-mask control signals to configure permutation circuitry for performing permutation operation on an input operand. The bit-mask identifies within the input operand the first group of data elements having a first ordering and a second group of data elements having a second ordering and the permutation operation is such that it preserves one of the first ordering and the second ordering but changes the other of the first ordering and the second ordering.
摘要翻译： 提供了一种用于处理数据的装置，其包括具有用于执行置换操作的置换电路的处理电路，具有用于存储数据的多个寄存器的寄存器组和响应于程序指令控制处理电路执行数据处理操作的控制电路。 控制电路被布置为响应于控制生成指令，以根据位掩码控制信号来产生以配置用于对输入操作数执行置换操作的置换电路。 位掩码在输入操作数内识别具有第一排序的第一组数据元素和具有第二排序的第二组数据元素，并且置换操作使得其保留第一排序和第二排序之一，但是改变 第一个订购中的另一个和第二个订购。
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10.发明申请公开(公告)号：US20100274990A1
公开(公告)日：2010-10-28
申请号：US12585573
申请日：2009-09-17
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30065 , G06F9/3893
摘要： An apparatus and method for performing SIMD multiply-accumulate operations includes SIMD data processing circuitry responsive to control signals to perform data processing operations in parallel on multiple data elements. Instruction decoder circuitry is coupled to the SIMD data processing circuitry and is responsive to program instructions to generate the required control signals. The instruction decoder circuitry is responsive to a single instruction (referred to herein as a repeating multiply-accumulate instruction) having as input operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicative of a plurality of iterations required, to generate control signals to control the SIMD processing circuitry. In response to those control signals, the SIMD data processing circuitry performs the plurality of iterations of a multiply-accumulate process, each iteration involving performance of N multiply-accumulate operations in parallel in order to produce N multiply-accumulate data elements. For each iteration, the SIMD data processing circuitry determines N input data elements from said first vector and a single coefficient data element from the second vector to be multiplied with each of the N input data elements. The N multiply-accumulate data elements produced in a final iteration of the multiply-accumulate process are then used to produce N multiply-accumulate results. This mechanism provides a particularly energy efficient mechanism for performing SIMD multiply-accumulate operations, as for example are required for FIR filter processes.
摘要翻译： 用于执行SIMD乘法累加操作的装置和方法包括响应于控制信号的SIMD数据处理电路，以对多个数据元素并行地执行数据处理操作。 指令解码器电路耦合到SIMD数据处理电路，并且响应于程序指令以产生所需的控制信号。 指令解码器电路响应于具有作为输入操作数的输入数据元素的第一向量，系数数据元素的第二向量和指示多个的标量值的单个指令（这里称为重复乘法累加指令） 以产生控制信号以控制SIMD处理电路。 响应于这些控制信号，SIMD数据处理电路执行多次累积处理的多次迭代，每次迭代涉及并行执行N次乘法运算，以产生N个乘法累加数据元素。 对于每次迭代，SIMD数据处理电路从所述第一向量确定N个输入数据元素，并且从第二向量确定要与N个输入数据元素中的每一个相乘的单个系数数据元素。 然后，在乘法累加过程的最终迭代中产生的N个乘法累加数据元素用于产生N个乘法累加结果。 该机制提供了用于执行SIMD乘法累加操作的特别高效的机制，例如FIR滤波器处理所需要的。
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